A 24GHz low-power CMOS RF receivers for indoor wireless application is developed in this paper. This paper presents a novel approach to integrate the RF front-end circuits, and realizes the manufacture of SoC (System on a Chip) design. The proposed RF IC includes a low-noise amplifier (LNA), a down-conversion mixer, a voltage-controlled oscillator (VCO) and a variable gain amplifier (VGA). For the demands of a low-power design, the LNA and VCO were designed with current-reused technology for lowering the dc power consumption, and the current-bleeding approach was adopted in mixer design for boosting its conversion gain, respectively. The proposed 24GHz CMOS RF receiver achieves the overall conversion gain of 23.4dB with noise figure of 5.4dB, and the total power consumption is only 31.65mW. Compared to the other papers published over the past few years, this paper exhibits a better potential in low-power design than other receivers applied in the same frequency band.

We apply the adaptive-order global Lanczos (AOGL) to generate the MIMO macromodel of high-speed VLSI interconnects. Theoretical foundations of the AOGL method for multiple point moment matching are investigated. In addition, the order selection of the reduced system was discussed. Experimental result on practical large-scale interconnect designs demonstrate that the reduced system generated by the AOGL method has better coherence to the original system both in time domain and in frequency domain. It has illustrated the feasibility and the efficiency of the AOGL method.

We present the global Lanczos algorithm for solving the RLCG interconnect circuits in this paper. This algorithm is an extension of the standard Lanczos algorithm for systems with multi-input multi-output (MIMO). A new matrix Krylov subspace will be developed first. By employing the congruence transformation with the matrix Krylov subspace, the two-side oblique projection-based method can be used to construct a reduced-order system. It will be shown that the system moments is still matched. The error of the 2q-th order system moment will be derived analytically. Finally, simulation results on both frequency domain and time domain will illustrate the feasibility and the efficiency of the proposed method.

We propose the global Arnoldi algorithm for MIMO RLCG interconnect model order reductions. This algorithm is an extension of the standard Arnoldi algorithm for systems with multi-inputs and multi-outputs (MIMO). By employing the congruence transformation with the matrix Krylov subspace, the one-sided projection method can be used to construct a reduced-order system. Two kinds of reduced systems using the global Arnoldi algorithm are proposed. The first q-th order of these reduced systems' moments is still preserved. The transfer matrix residual error of the reduced system is also derived analytically. Experimental results demonstrate the feasibility and the effectiveness of the proposed method.

In this paper, we propose the new two-dimensional (2-D) systolic-array structures of IIR/FIR digital filters without global broadcast by the different derivation and another systolic transformation. For more practical considerations, we further provide a detailed block diagram of a 2-D FIR filter using a recently proposed multiplier to reduce the roundoff quantization error in the logic-gate level. These proposed systolic structures amenable to VLSI implementation permit the 2-D input sequence to be scanned in row-wise mode and locally broadcast one value each clock per delay element.

In this work, we develop an optimized binary tree-level rule for the design of a systolic array structure of a delay least mean square (DLMS) adaptive filter. Using the developed method, a higher convergence rate can be obtained without sacrificing the properties of the systolic array structure. Also, based on the optimized tree rule, the user can easily design any even-number tap adaptive system with minimum delay and high regularity under the constraints of maximum driving and the total number of taps.

In this paper, we propose two new methods for computing the transient sensitivities of large scale MOSFET circuits, which exploit the relaxation-based circuit simulation techniques, the waveform relaxation (WR) method and the iterated timing analysis (ITA) method. Sufficient conditions are stated and proven, which are quite mild for MOSFET circuits, for convergence of these new methods. A pruning scheme, which prunes the sensitivity circuits, takes the positions of the design parameters as well as the outputs of interest into account and saves any redundant subcircuit computation even though that subcircuit may not be latent. By modifying the original WR and ITA algorithms, we also present practical computational algorithms which can process multiple design parameters. These practical algorithms retain most of the structures of the original algorithms, which can easily be implemented into available relaxation-based circuit simulators. These new methods have been implemented and the experimental results for several circuits are shown to demonstrate their effectiveness.>

No abstract available.

An improved analytical model for short-channel MOSFETs which is valid in all regions of operation with both the continuous drain current and the output conductance by introducing a source-drain series resistance dependent scaling factor is proposed for analog/digital circuit simulation. This model considers all second-order effects for an accurate determination of the pinchoff point location without internal numerical iterations. Comparisons with experimental data for submicron devices confirm the model validity. Furthermore, a simple interpolation is also presented to maintain the continuous slope of the output conductance and its effect on the drain current is demonstrated to be acceptable.>

An H-V alternating router based on the concurrent H (horizontal) and V (vertical) tile expansions is presented. The router is modeled by a sequence of alternating H and V corner-stitching space tiles, where the expansion direction is controlled by a heuristic evaluation function using the A* technique and the damping concept. Tile growing is governed by the following three factors: constrained expansion area, limited expansion depth, and oriented expansion direction. All the H-V tile expansion operations can be easily performed on a specially designed net-forest structure. It is shown that this approach generates nearly optimal connection paths with a minimum number of bends and always guarantees a feasible solution if such a path exists. The performance of this router is better than that of H-only tile-expansion routers. This router is also well suited for wiring hierarchical modules with the metal-metal matrix technology and can be extended to multilayer layouts.>

Article Free Access Share on Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems Authors: Sung-Chuan Fang Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C.View Profile , Kuo-En Chang Department of Information and Computer Education, National Taiwan Normal University, Taipei, Taiwan, R.O.C. Department of Information and Computer Education, National Taiwan Normal University, Taipei, Taiwan, R.O.C.View Profile , Wu-Shiung Feng Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C.View Profile , Sao-Jie Chen Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C.View Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 60–65https://doi.org/10.1145/127601.127629Published:01 June 1991Publication History 15citation536DownloadsMetricsTotal Citations15Total Downloads536Last 12 Months43Last 6 weeks6 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A method to compute the transient sensitivities for waveform relaxation (WR)-based circuit simulation is presented. By partitioning the circuit into subcircuits, one computes the transient sensitivities for each 'active' subcircuit and then propagates the calculated results to the succeeding subcircuits to iterate for the entire sensitivities. Experimental results show that the proposed method provides sensitivity waveforms which are very close to those obtained by the direct method in a reasonably short time, and works well even though the circuit contains feedback loops.>

A graph-generating algorithm and the experimental results of a hierarchical mask-layout-compaction scheme based on a plane-sweep algorithm, a fast region-query and a space-efficient data structure called the hierarchical multiple-storage quad tree are presented. For a mask-layout design, a rectangle is used as the primary element of the layout. Hence, in the hierarchical mask-compaction scheme, the graph-generating algorithm is based on the edges of rectangles rather than the central lines of symbols for the symbolic-compaction design. The plane-sweep algorithm is also called a dynamic event scheduling algorithm and can be applied to solve some other problems in the field of computational geometry and image processing. The efficiencies of the plane-sweep algorithm and the graph-generating algorithm are dependent on the region-query operations of the spatial data structure. By using the improved multiple storage quad tree as the spatial data structure in the system, the mask-layout compactor has been accomplished in a practically linear time performance in terms of the rectangles in the source layout.>

A rule-based system, to be used in place of the conventional approaches using algorithms, is proposed to explore the feasibility of using expert system technology to automate the compaction process by reasoning about the layout design using the sophisticated expert rules contained in its knowledge base. It has been demonstrated that, given a process-independent mask layout, the design rules, user specified constraints, and circuit electrical requirements can be checked over and rearranged into an optimized state. The system considered consists of approximately 100 Kbytes of source code and contains 120 rules. The compactor is written in a combination of the Lisp and OPS5 languages.>