EDBT 2026 Demo / reviewers in the wild / expert
Donald M. Schuler
dblp:56/10971
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 1984
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 98% Integrated circuit design · 2% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
logic simulation |
0.0 | 1 | 1984 | THEMIS logic simulator - a mix mode, multi-level, hierarchical, interactive digital circuit simulator · DAC 1984 |
Electronic design automation › hardware simulation › multilevel simulation
mixed-mode simulation |
0.0 | 1 | 1984 | THEMIS logic simulator - a mix mode, multi-level, hierarchical, interactive digital circuit simulator · DAC 1984 |
Electronic design automation › hardware simulation
multilevel simulation |
0.0 | 1 | 1984 | THEMIS logic simulator - a mix mode, multi-level, hierarchical, interactive digital circuit simulator · DAC 1984 |
Electronic design automation
hardware verification and test |
0.0 | 2 | 1977 | An efficient method of fault simulation for digital circuits modeled from boolean gates and memories · DAC 1977 Random test generation using concurrent logic simulation · DAC 1975 |
Electronic design automation › hardware verification and test
fault simulation |
0.0 | 1 | 1977 | An efficient method of fault simulation for digital circuits modeled from boolean gates and memories · DAC 1977 |
Electronic design automation
interactive simulation |
0.0 | 1 | 1984 | THEMIS logic simulator - a mix mode, multi-level, hierarchical, interactive digital circuit simulator · DAC 1984 |
Electronic design automation › hardware verification and test › test generation
random test generation |
0.0 | 1 | 1975 | Random test generation using concurrent logic simulation · DAC 1975 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1977 | An efficient method of fault simulation for digital circuits modeled from boolean gates and memories · DAC 1977 |
Methods — techniques the papers use, named apart from their topics
memory modeling · 0.0concurrent logic simulation · 0.0boolean gate modeling · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1984 | THEMIS logic simulator - a mix mode, multi-level, hierarchical, interactive digital circuit simulator
Mahesh H. Doshi, Roderick B. Sullivan, Donald M. Schuler |
DAC | 3 |
| 1977 | An efficient method of fault simulation for digital circuits modeled from boolean gates and memories
Donald M. Schuler, Roger K. Cleghorn |
DAC | 1 |
| 1975 | Random test generation using concurrent logic simulation
Donald M. Schuler, Ernst G. Ulrich, Thomas E. Baker, Susan P. Bryant |
DAC | 1 |