Demo Data from EDBT 2026 / reviewers in the wild / expert
Vladimir Friedman
dblp:56/11151
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 1988
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Integrated circuit design · 80% Processor architecture and microarchitecture · 20% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › microprocessor design
bit-slice architecture |
0.0 | 1 | 1988 | A bit-slice architecture for sigma-delta analog-to-digital converters · IEEE J. Sel. Areas Commun. 1988 |
Integrated circuit design › analog and mixed-signal circuits
data converters |
0.0 | 1 | 1988 | The structure of the limit cycles in sigma delta modulation · IEEE Trans. Commun. 1988 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1988 | A bit-slice architecture for sigma-delta analog-to-digital converters · IEEE J. Sel. Areas Commun. 1988 |
Integrated circuit design › analog and mixed-signal circuits
mixed-signal circuit design |
0.0 | 1 | 1988 | A bit-slice architecture for sigma-delta analog-to-digital converters · IEEE J. Sel. Areas Commun. 1988 |
Integrated circuit design › analog and mixed-signal circuits › data converters
sigma-delta modulator |
0.0 | 1 | 1988 | The structure of the limit cycles in sigma delta modulation · IEEE Trans. Commun. 1988 |
Methods — techniques the papers use, named apart from their topics
number theory · 0.0noise analysis · 0.0decimation · 0.0IIR filtering · 0.0FIR filtering · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1988 | A bit-slice architecture for sigma-delta analog-to-digital convertersabstractThe sigma-delta analog-to-digital converters is based on filtering and undersampling by the digital section of the one-bit output stream coming from the modulation. The structure of this section, consisting of a sine cubic FIR filter decimator followed by an IIR decimator section, is discussed. It is shown that from both signal processing and hardware implementation viewpoints it is advantageous to have the decimation factor of the first stage as large as possible. A bit-slice implementation of the decimation stages is given. It can be easily expanded when higher bit resolutions are required.> Vladimir Friedman, Douglas M. Brinthaupt, De-Ping Chen, Timothy W. Deppa, John P. Elward Jr., Evelyn M. Fields, Hanafy Meleis |
IEEE J. Sel. Areas Commun. | 1 |
| 1988 | The structure of the limit cycles in sigma delta modulationabstractIt is shown that when the input to a sigma-delta modulator is a DC level that can be expressed as a rational number b/a, when normalized with respect to the quantizer step, the output bit string is periodic with a period that is multiple of the denominator a. On the basis of number theory, the structure of these cycles for single-loop modulators is determined and the noise contribution is computed. Around such levels the noise has two peaks, for which the maximum value and the width are proportional to the relative signal bandwidth and to the inverse of the period of the cycle, respectively. The effect of the limit cycles on the performance of the A/D and D/A converters using sigma-delta modulation is discussed. A comparison between single-loop and double-loop modulators from the point of view of this phenomena is made.> Vladimir Friedman |
IEEE Trans. Commun. | 1 |