EDBT 2026 Demo / reviewers in the wild / expert
Sandeep Dasgupta
dblp:56/11498
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 2020
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
2 papers |
Programming languages and type systems · 56% Program analysis · 30% Compilers and program optimization · 15% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Programming languages and type systems › language semantics
formal semantics |
0.8 | 2 | 2020 | Scalable validation of binary lifters · PLDI 2020 A complete formal semantics of x86-64 user-level instruction set architecture · PLDI 2019 |
Programming languages and type systems › language semantics › formal semantics
instruction set semantics |
0.8 | 2 | 2020 | Scalable validation of binary lifters · PLDI 2020 A complete formal semantics of x86-64 user-level instruction set architecture · PLDI 2019 |
Program analysis
binary analysis |
0.4 | 1 | 2020 | Scalable validation of binary lifters · PLDI 2020 |
Program analysis › binary analysis
binary lifting |
0.4 | 1 | 2020 | Scalable validation of binary lifters · PLDI 2020 |
Compilers and program optimization › verified compilation
translation validation |
0.4 | 1 | 2020 | Scalable validation of binary lifters · PLDI 2020 |
Processor architecture and microarchitecture
instruction set architecture |
0.4 | 1 | 2019 | A complete formal semantics of x86-64 user-level instruction set architecture · PLDI 2019 |
Processor architecture and microarchitecture › instruction set architecture › CISC
x86-64 |
0.4 | 1 | 2019 | A complete formal semantics of x86-64 user-level instruction set architecture · PLDI 2019 |
Methods — techniques the papers use, named apart from their topics
instruction-level testing · 0.8executable semantics · 0.8semantic equivalence checking · 0.4graph isomorphism · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | Scalable validation of binary liftersabstractValidating the correctness of binary lifters is pivotal to gain trust in binary analysis, especially when used in scenarios where correctness is important. Existing approaches focus on validating the correctness of lifting instructions or basic blocks in isolation and do not scale to full programs. In this work, we show that formal translation validation of single instructions for a complex ISA like x86-64 is not only practical, but can be used as a building block for scalable full-program validation. Our work is the first to do translation validation of single instructions on an architecture as extensive as x86-64, uses the most precise formal semantics available, and has the widest coverage in terms of the number of instructions tested for correctness. Next, we develop a novel technique that uses validated instructions to enable program-level validation, without resorting to performance-heavy semantic equivalence checking. Specifically, we compose the validated IR sequences using a tool we develop called Compositional Lifter to create a reference standard. The semantic equivalence check between the reference and the lifter output is then reduced to a graph-isomorphism check through the use of semantic preserving transformations. The translation validation of instructions in isolation revealed 29 new bugs in McSema – a mature open-source lifter from x86-64 to LLVM IR. Towards the validation of full programs, our approach was able to prove the translational correctness of 2254/2348 functions taken from LLVM’s single-source benchmark test-suite. Sandeep Dasgupta, Sushant Dinesh, Deepan Venkatesh, Vikram S. Adve, Christopher W. Fletcher |
PLDI | 1 |
| 2019 | A complete formal semantics of x86-64 user-level instruction set architectureabstractWe present the most complete and thoroughly tested formal semantics of x86-64 to date. Our semantics faithfully formalizes all the non-deprecated, sequential user-level instructions of the x86-64 Haswell instruction set architecture. This totals 3155 instruction variants, corresponding to 774 mnemonics. The semantics is fully executable and has been tested against more than 7,000 instruction-level test cases and the GCC torture test suite. This extensive testing paid off, revealing bugs in both the x86-64 reference manual and other existing semantics. We also illustrate potential applications of our semantics in different formal analyses, and discuss how it can be useful for processor verification. Sandeep Dasgupta, Daejun Park 0001, Theodoros Kasampalis, Vikram S. Adve, Grigore Rosu |
PLDI | 1 |