The high-speed WLAN is standardized by the IEEE 802.11 task group n. For wireless access in vehicular environments, it is standardized as IEEE 802.11p which is based on 802.11n. Devices for wireless communication based on 802.11n draft are widely spreading in the world market now, but there is no report available which discusses the performance of such 802.11n devices. In this poster, we introduce a basic performance evaluation of IEEE 802.11 devices. We show experimental results using 802.11n draft 2.0 devices which are available on the market. In particular, we tested the throughput performance and the coverage range of IEEE 802.11n devices in outdoor environments during a car to car communication scenario. The experimental results show the limits of using IEEE 802.11n devices in vehicular networks.

We present XLearner, a novel tool that helps the rapid development of XML mapping queries written in XQuery. XLearner is novel in that it learns XQuery queries consistent with given examples (fragments) of intended query results. XLearner combines known learning techniques, incorporates mechanisms to cope with issues specific to the XQuery learning context, and provides a systematic way for the semiautomatic development of queries. We describe the XLearner system. It presents algorithms for learning various classes of XQuery, shows that a minor extension gives the system a practical expressive power, and reports experimental results to demonstrate how XLearner outputs reasonably complicated queries with only a small number of interactions with the user.

A wireless adhoc network consists of mobile nodes that may move often. The mobility of nodes results in a change in routes, requiring some mechanism for determining new routes. A number of routing protocols have already been proposed for wireless Ad-hoc networks. In these conventional protocols, transmission power of each node is kept constant This paper proposes an approach to control transmission power to improve the performance of routing protocols. By controlling power, the proposed Power Control Routing (PCR) improves the network capacity and power consumption. Simulation experiments show that PCR has high network capacity and low power consumption.

This paper describes the design and performance of a tightly-coupled shared-memory coherent cache optimized for the execution of parallel logic programming architectures. The cache utilizes a copy-back write-allocation protocol having five states and a hardware lock mechanism. Optimizations for logic programming are introduced in four software-controlled memory access commands: direct-write, exclusive-read, read-purge, and read-invalidate. In this paper we describe these operations and present simulated measurements showing their performance advantage for an architecture of the committed-choice language KL1. The cache optimizations also improve the performance of non-committed-choice languages, such as OR-parallel Prolog. A version of the cache design described here is currently being implemented for ICOT's Parallel Inference Machine (PIM).