We present ExaDigiT, an open-source framework for developing comprehensive digital twins of liquid-cooled supercomputers. It integrates three main modules: (1) a resource allocator and power simulator, (2) a transient thermo-fluidic cooling model, and (3) an augmented reality model of the supercomputer and central energy plant. The framework enables the study of “what-if” scenarios, system optimizations, and virtual prototyping of future systems. Using Frontier as a case study, we demonstrate the framework’s capabilities by replaying six months of system telemetry for systematic verification and validation. Such a comprehensive analysis of a liquid-cooled exascale supercomputer is the first of its kind. ExaDigiT elucidates complex transient cooling system dynamics, runs synthetic or real workloads, and predicts energy losses due to rectification and voltage conversion. Throughout our paper, we present lessons learned to benefit HPC practitioners developing similar digital twins. We envision the digital twin will be a key enabler for sustainable, energy-efficient supercomputing.

As the power demands of supercomputers continue to grow, so do the demands of the mechanical cooling systems that support the infrastructure and building in which the supercomputers reside. Planning for the cooling systems and their mechanical controls are an intrinsic part of any new supercomputer installation. To support the design and commissioning of the mechanical control systems, the Energy Efficient High Performance Computing Working Group (EE HPC WG) Cooling Controls is developing a template for an OPR (Owner Project Requirements) document. The design of the template, while pursued by a small team, leveraged the expertise of the broad membership of the EE HPC WG through surveys and feedback sessions. As a result, the OPR template includes not only a suggested structure, and a checklist of topics that a site might consider including in the document, but also many real-world examples of how the topics were addressed in previous projects. Finally, the Mechanical Controls OPR template is being developed in parallel with other templates focused on other aspects of a supercomputer installation. These templates are intended to improve the efficiency and comprehensiveness of the programming (pre-design) phase of project execution and provide the engineering and design team with better clarity of the facility infrastructure capabilities, expandability, and performance requirements. The intended result is improved construction documents (Basis-of-Design, drawings and specifications) that support the project goals and objectives including reliability, resiliency, and energy efficiency expectations of the HPC facility.

Sun and Luo recently showed that if the vector-space single-beam interference alignment problem for a K-user, L-carrier interference channel is feasible, then K ≤ 2L - 2. We prove the converse, that if K ≤ 2L - 2, then the problem is feasible, i.e., that the requisite beamformers do exist.

Modern FPGAs are used to implement a wide range of circuits, many of which have coarse-grained and fine-grained components. The ever-increasing size of these circuits places great demand on CAD tools to synthesize circuits faster and without loss in quality. Synthesizing coarse-grained components onto fine-grained FPGA resources is inefficient, and past attempts to optimize FPGAs for word-oriented datapaths have met with limited success. This paper presents a CAD flow to fully compile Verilog into a configuration bitstream for a new type of FPGA with time-multiplexed coarse-grained resources. We demonstrate two approaches with gains of 61x and 42x in synthesis time on average compared to QuartusII, but due to time-multiplexing and current synthesis limitations we achieve circuit speeds of 14x and 8.5x slower on average. We show the tools can also trade density for maximum clock frequency.

A computational circuit is custom-designed hardware which promises to offer maximum speedup of computationally intensive software algorithms. However, the practical needs to manage development cost and many low-level physical design details erodes much of the potential speedup by distracting attention away from high-level architectural design. Instead, designers need an inexpensive, processor-like platform where computational circuits can be rapidly synthesized and simulated. This enables rapid architectural evolution and mitigates the risk of producing custom hardware. In this paper we present a tool flow (RVETool) for compiling computational circuits into a massively parallel processor array (MPPA). We demonstrate the CAD runtime is on average 70x faster than FPGA tools, with a circuit speed 6.4x slower than FPGA devices. Unlike the fixed logic capacity of FPGAs, RVETool can trade area for simulation performance by targeting a wide range of processor cores.

Windows Error Reporting (WER) is a distributed system that automates the processing of error reports coming from an installed base of a billion machines. WER has collected billions of error reports in ten years of operation. It collects error data automatically and classifies errors into buckets, which are used to prioritize developer effort and report fixes to users. WER uses a progressive approach to data collection, which minimizes overhead for most reports yet allows developers to collect detailed information when needed. WER takes advantage of its scale to use error statistics as a tool in debugging; this allows developers to isolate bugs that could not be found at smaller scale. WER has been designed for large scale: one pair of database servers can record all the errors that occur on all Windows computers worldwide.

CAD tool designers are always searching for more benchmark circuits to stress their software. In this article we present a heuristic method to generate benchmark circuits specially suited for incremental place-and-route tools. The method removes part of a real circuit and replaces it with an altered version of the same circuit to mimic an incremental design change. The alteration consists of two steps: mutate followed by perturb . The perturb step exactly preserves as many circuit characteristics as possible. While perturbing, reproduction of interconnect locality, a characteristic that is difficult to measure reliably or reproduce exactly, is controlled using a new technique, ancestor depth control (ADC). Perturbing with ADC produces circuits with postrouting properties that match the best techniques known to-date. The mutate step produces targetted mutations resulting in controlled changes to specific circuit properties (while keeping other properties constant). We demonstrate one targetted mutation heuristic, scale, to significantly change circuit size with little change to other circuit characteristics. The method is simple enough for inclusion in a CAD tool directly, and fast enough for use in on-the-fly benchmark generation.

FPGA architects are always searching for more benchmark circuits to stress CAD tools and device architectures. In this paper we present a new method to generate benchmark circuits by removing part of a real circuit and replacing it with a synthetic clone. This replacement or stitching process can easily introduce combinational loops if the synthetic circuit contains an input-to-output dependence that was not in the original subcircuit it is replacing. We show that this can be expressed as the graph monomorphism problem, and that a solution to that problem gives a precise stitching assignment that is cycle-free. This technique can be used to create new benchmark circuits that are identical to the original circuit except for small, local changes. The resulting semi-synthetic benchmarks are ideal for testing incremental place and route tools.

FPGA architects are always searching for more benchmark circuits to stress CAD tools and device architectures. In this paper we present a new heuristic to generate benchmark circuits specifically for incremental place and route tools. The method removes part of a real circuit and replaces it with a modified version of the same circuit to mimic an incremental design change. The generation procedure exactly preserves key circuit characteristics and achieves a post-routing channel width, critical path, and wire length that closely approximates those of the original circuit. Additionally, the method is fast and thus is suitable for use in on-the-fly benchmark generation

This paper describes a fixed-weight Hamming binary neural classifier chip suitable for applications where high-speed operation is required. The circuit uses switched current-mode techniques throughout and achieves classification in one forward pass through the network. The chip was realised in 2.4 /spl mu/m n-well CMOS technology and was designed to recognise the integers 0-9. It achieved a classification rate of 10 MHz without any observable tendency to misclassification or instability.>