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Shin-ichiro Mori

dblp:56/2930 · DBLP profile ↗
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10ranked-venue papers
2as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 2 first-authorArtificial intelligence and machine learning · 2Software engineering, systems software and programming languages · 2Graphics, computer vision, multimedia, augmented reality and games · 1Human-computer interaction and ubiquitous computing · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer graphics and multimedia
1 paper
Computer animation and physical simulation · 50% Geometric modeling and processing · 50%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 80% Memory systems · 20%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Geometric modeling and processing › shape modeling › shape editing
mesh editing
0.112008
Vertex-preserving Cutting of Elastic Objects · VR 2008
Computer animation and physical simulation › deformable body simulation
soft tissue simulation
0.112008
Vertex-preserving Cutting of Elastic Objects · VR 2008
Processor architecture and microarchitecture › instruction scheduling
dynamic instruction scheduling
0.012001
A high-speed dynamic instruction scheduling scheme for superscalar processors · MICRO 2001
Processor architecture and microarchitecture
instruction scheduling
0.012001
A high-speed dynamic instruction scheduling scheme for superscalar processors · MICRO 2001
Memory systems
cache coherence
0.011993
A distributed shared memory multiprocessor ASURA: memory and cache architecture · SC 1993
Memory systems › shared memory
distributed shared memory
0.011993
A distributed shared memory multiprocessor ASURA: memory and cache architecture · SC 1993
Processor architecture and microarchitecture
multiprocessor architecture
0.011993
A distributed shared memory multiprocessor ASURA: memory and cache architecture · SC 1993
Processor architecture and microarchitecture
superscalar processor
0.012001
A high-speed dynamic instruction scheduling scheme for superscalar processors · MICRO 2001

Methods — techniques the papers use, named apart from their topics

topological update scheme · 0.1finite element method · 0.1dynamic scheduling scheme · 0.0simulation · 0.0hierarchical directory · 0.0
YearPublicationVenuePosition
2019 An Multi-client Web-based Interactive HCI for Interactive Supercomputing
abstract
Importance of the real-time data analysis even in the HPC area rapidly increase in the recent data intensive science. Once the real-time data analysis becomes available, the interactive feedback to the data source will be happening to make thing improve. In order to realize such an environment for scientific simulation, the framework for interactive supercomputing has been developed so far. However, user interaction of that framework was limited to a certain closed environment. In this paper, web-based ubiquitous interface that allows simultaneous sharing of on-going simulation among multiple users is proposed.
Yuya Yamamoto, Fumitaka Arakawa, Ayaka Fujii, Shinji Fukuma, Shin-ichiro Mori
SNPD5
2016 A real-time GPU-based coupled fluid-structure simulation with haptic interaction
abstract
Time series scientific simulation on supercomputers generates huge amounts of data at each time step. In the big data era, these data become impossible to be stored anymore, so simultaneous analysis of these data is strongly demanded. In order to realize such an on-the-fly intuitive analysis of simulation, this paper showcases a multimodal visualization and steering system with visual and haptic interfaces for a real-time GPU-based coupled fluid-structure simulation. Since the nature of touching sense of human beings requires extremely fast and continuous refreshing to form authentic feeling, parallel techniques were utilized to speed up haptic updating to around one millisecond. A middle-layer interface for a haptic device was developed to realize the ease of use of this device. Furthermore, a model of palpation was proposed to allow users to touch, push and sense the dynamic fluid motion inside a deformable tube.
Jiachao Zhang, Shunpei Yuasa, Shinji Fukuma, Shin-ichiro Mori
ICIS4
2012 Prototype Implementation of a GPU-based Interactive Coupled Fluid-Structure Simulation
abstract
This paper reports a prototype implementation of 3D Fluid-Structure Simulation. In this implementation, heartbeat fluid flows inside a rectangular tube where the operator can interactively change the width of the tube. In order to achieve interactive simulation speed, some parts of the simulation is accelerated by GPU. For further improvement of the simulation speed, two techniques have been examined: the first one reduces the communication between CPU and GPU, and the second one offloads a whole fluid flow simulation onto GPU.
Ryota Henmi, Yusuke Nishimura, Hiroaki Suzuki, Shinji Fukuma, Shin-ichiro Mori, Akinori Yamaguchi, Shinji Tomita
SNPD5
2008 Vertex-preserving Cutting of Elastic Objects
abstract
This paper proposes vertex-preserving cutting methods on finite element models for interactive soft tissue simulation. Unlike existing methods, we aim to shape variety of incisions using only initial vertices of tetrahedral meshes. Neither tetrahedral decomposition nor vertex creation is used. The number of vertices is preserved. This avoids increase of computation cost as well as allows fast update of physical status of finite element models. To preserve 3D shape and sharp feature of initial meshes through on-the-fly mesh modification, constraints are introduced to the topological update scheme. In our model, the size of stiffness matrix is constant. Our framework efficiently simulates several varieties of smooth incisions with sufficient quality for surgical simulation, and also achieves interactive performance in complex meshes with thousands of elements.
Megumi Nakao, Kotaro Minato, Naoto Kume, Shin-ichiro Mori, Shinji Tomita
VR4
2001 A high-speed dynamic instruction scheduling scheme for superscalar processors
Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori
MICRO6
1996 Amon2: A Parallel Wire Routing Algorithm on a Torus Network Parallel Computer
Hesham Keshk, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita
International Conference on Supercomputing2
1995 A proposal of self-cleanup cache
Shin-ichiro Mori, Masahiro Goshima, Hiroshi Nakashima, Shinji Tomita
PACT1
1995 Amon: A Parallel Slice Algorithm for Wire Routing
abstract
In thk paper a new parallel global and detailed wire routing algorithm called "Amen" is introduced.Both of them are done in parallel using different processor elements (PEs).We introduce a new way of dividing the multilayer grid into layers, and dividing layers into slices.Each PE, in the detailed routing, has a responsibility for one or more slice.This way of division obtains a high degree of parallelism.A new detailed routing algorithm which routes nets under the condition that these net paths do not prevent other nets from being routed later is also introduced.Amen gives high routing quality by using fewer vias and shorter wire length than the other algorithms.The results show that this algorithm obtains higher connection ratio than maze running algorithm.
Hesham Keshk, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita
International Conference on Supercomputing2
1993 A distributed shared memory multiprocessor ASURA: memory and cache architecture
abstract
ASURA is a large scale, chwier-based, distributed, shared memory, multiprocessor being developed at Kyoto University and Kubota Corporation.Up to 128 clusters are interconnected to form an ASURA system of up to 102d processors.The basic concept of the ASURA design is to take advantage of the hierarchical structure of the system.Implementing this concept, a large shared cache is piaced between each cluster and the inter-ciuster network.The shared cache and the shared memories distributed among the clusters form part of ASURA's hierarchical memory architecture, providing various unique features to ASURA.In this paper, the hierarchicalmemory architecture of ASURA and its unique cache coherence scheme, including a proposal of a new hierarchical directory scheme, are described wzth some simulation results.Permission tocopy without fes all or pan of Ibis .n81e&al is granted, pmvidd that tbe copies me not made or dishiluted fw dim commenial advantage, the ACMwpyrisbtmalice and tbe title of the F.Iblication and its date appesr, snd notice is given that cqying is by permission of tbe Association forComputing Mschimy.ToCOPY ciherwi%csto republih.requires a fee Snlvcu Specilic pmnissian.
Shin-ichiro Mori, Hideki Saito 0001, Masahiro Goshima, Mamoru Yanagihara, Takashi Tanaka, David Fraser, Kazuki Joe, Hiroyuki Nitta, Shinji Tomita
SC1
1989 The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures
abstract
The reconfigurable parallel processor system under development at Kyushu University is an MIMD-type multiprocessor which consists of N processing-elements (currently N is 128) fully connected by S N × N crossbar networks (currently S is 1). Each PE (Processing Element) employs a Fujitsu SPARC MB86900/10 chip-set, a Weitek WTL1164/65 chip-set, an MMU (Memory Management Unit) with 64K bytes of cache, 4M bytes of memory, and an MCU (Message Communication Unit). The modular 128 × 128 crossbar network is implemented by arranging 256 identical 8 × 8 crossbar LSI-modules in a 16 × 16 matrix form. The full 128-PE configuration achieves supercomputer levels of performance by providing 1.28 GIPS and 205 MFLOPS of computing power, 512M bytes of memory, and 2.56G bytes/s of inter-PE communication bandwidth. At the same time, it exploits unique reconfigurability in the memory and intercommunication architectures. By utilizing these two types of reconfigurability, we believe that the system can be effectively tailored to a wide spectrum of applications such as numerical computation, image processing, computer graphics, artificial intelligence, neurocomputing, and so on.
Kazuaki J. Murakami, Shin-ichiro Mori, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita
ICS2