It is important to utilize the idle time of a workload to improve the system performance. In the article, we will explore multiple idle time detection methods to predict the idle time of the real I/O workloads. The objective is to build a stable idle time detection platform by investigating the impact of multiple representative methods to pursue a more stable prediction accuracy. The experimental results show that the prediction accuracy of the proposed platform can be stable between 60% and 80%.

In recent years, the intermittent computing devices have become increasingly widespread and result in a greater demand for storage space. In particular, NAND flash memory is well-suited as a storage medium for the intermittent computing devices, but its "out-of-place" update characteristic leads to a garbage collection (GC) mechanism to reclaim invalid pages when the number of free pages becomes insufficient. The previous studies have shown that a suitable separation of hot and cold data (i.e., a clustering method) can significantly reduce the overhead of garbage collection and improve the performance. However, the previous studies are not suitable for the intermittent computing devices that are equipped with the limited volatile memory space and very low computing power. Therefore, we will propose a hash-based clustering system software for the intermittent computing devices to provide a suitable separation of hot and cold data. The experimental results show that the proposed method with low computational time and low volatile memory space can achieve a reduction of 8% 10%, 8% 10%, 10%, and 5% 7%, in page reads, page writes, block erases, average number of erases per block, and a reduction of 8% 11% in write amplification when compared to the previous methods (such as a DBSCAN-based clustering method and a K-means clustering method). Additionally, the proposed method can efficiently recover to the most recent state when the intermittent computing devices experience power outages.

DM-SMR (device-managed shingled magnetic recording) disks allocate a portion of disk space as the persistent cache (PC) to address the issue of overlapping tracks during data updates. When the PC space becomes insufficient, a space cleaning is triggered to reclaim its invalid space. However, the space cleaning is time-consuming and contributes to the long-tail latency of DM-SMR disks. In the article, we will propose a space-grained cleaning method that leverages various idle periods to effectively reduce the long-tail latency of DM-SMR disks. The objective is to perform a proper space-grained cleaning for a suitable space region at an appropriate time period, thereby preventing delays in subsequent I/O requests and reducing the long-tail latency associated with DM-SMR disks. The experimental results demonstrate a substantial reduction in the long-tail latency of DM-SMR disks through the proposed method.

Nowadays, solid-state drives (SSDs) have become the best choice of storage devices because of its brilliant advantages such as small size, low-power consumption, shake resistance, fast access and non-volatility, when compared with hard-disk drives (HDDs). More and more scenarios adopt a multi-SSD architecture to improve performance and expand storage capacity, such as cloud services, database centers, distributed systems and virtualized environments. When multiple users (flows) are competing for shared multiple SSDs concurrently, if the multi-SSD architecture lacks a fairness strategy among multiple users, a user that takes up more resources can affect other users. Meanwhile, if the multi-SSD architecture lacks a load-balance strategy among multiple shared SSDs, some specific SSDs may receive too many I/O requests to degrade the performance and shorten the lifespan. Therefore, we will propose a state-aware method to consider flows with fairness on NVMe SSDs with load balance. According to experimental results, we can show that the proposed method can improve the fairness by 1.15x$\sim$1.19x and the load balance by 1.18x$\sim$3.15x on average, when compared to other methods.

Nowadays, TLC NAND flash memory has become a mainstream storage medium because of its large capacity and low cost. However, TLC NAND flash memory could have the reliability problem (such as the retention errors and the read disturb errors), as the cell capacity increases. Because the reasons of the retention errors and the read disturb errors are due to 8 different states in a TLC cell, we will propose a method to coordinate the retention errors, the read disturb errors and the Huffman coding on TLC NAND flash memory by removing some unsuitable states when different data accesses are considered. According to the experimental results, the proposed method can utilize the compression of the Huffman coding to improve the performance. In addition, the proposed method can also remove the unsuitable states that are susceptible to the retention errors and the read disturb errors to enhance the reliability of TLC NAND flash memory.

In recent years, solid-state drives (SSDs) that adopt NAND flash memory have been widely used as the main storage devices. In particular, NAND flash memory has a special feature of “out-of-place” updates to write the up-to-date data to a free page, and the corresponding old page will become invalid. When the number of free pages in SSDs is insufficient, garbage collection (GC) will be executed to reclaim the invalid pages in a block by erasing the block. Many studies have shown that a good hot/cold data separation (i.e., clustering) can greatly reduce the overhead of GC so as to improve the SSD performance. However, previous clustering methods usually use a static number of clusters or a fixed size of granularity (i.e., a fine-grained or a coarse-grained granularity), so they may not always perform well for different kinds of workloads. Therefore, we propose a granularity-based clustering method to adaptively adjust the size of granularity groups for an appropriate number of clusters at runtime according to the update distances of logical addresses. According to the experimental results, we can improve SSD performance by reducing the overhead of GC and decrease the write amplification. Furthermore, we can show that the proposed method can utilize a fine-grained granularity to retain the record accuracy of update distances and also utilize a coarse-grained granularity to reduce the space required to record update distances.

Although NAND flash memory has the advantages of small size, low-power consumption, shock resistance, and fast access speed, NAND flash memory still faces the problems of “out-of-place updates,” “garbage collection,” and “unbalanced execution time” due to its hardware limitations. Usually, a flash translation layer (FTL) can maintain the mapping cache (in limited DRAM space) to store the frequently accessed address mapping for “out-of-place updates” and maintain the read/write buffer (in limited DRAM space) to store the frequently accessed data for “garbage collection” and “unbalanced execution time”. In this article, we will propose a write-related and read-related DRAM allocation strategy inside solid-state drives (SSDs). The design idea behind the write-related DRAM allocation method is to calculate the suitable DRAM allocation for the write buffer and the write mapping cache by building a statistical model with a minimum expected value of writes for NAND flash memory. To further reduce reads in NAND flash memory, the design idea behind the read-related DRAM allocation method is to adopt a cost-benefit policy to reallocate the proper DRAM space from the write buffer and the write mapping cache to the read buffer and the read mapping cache, respectively. According to the experimental results, we can demonstrate that the proposed write-related and read-related DRAM allocation strategy can reduce more reads/writes in NAND flash memory than other methods to improve the response time.

Nowadays, solid-state drives (SSDs) have become the best choice of storage devices, when compared with hard-disk drives (HDDs). More and more scenarios adopt a multi-SSD architecture to improve performance and expand storage capacity for cloud services, database centers, distributed systems and virtualized environments. When multiple users (flows) are competing for shared multiple SSDs concurrently, if the multi-SSD architecture lacks a fairness strategy among multiple users, a user that takes up more resources can affect other users. Meanwhile, if the multi-SSD architecture lacks a load-balance strategy among multiple shared SSDs, some specific SSDs may receive too many I/O requests to degrade the performance and shorten the lifespan. Therefore, we will propose a state-aware method to consider flows with fairness on NVMe SSDs with load balance.

With the progress of the manufacturing process, NAND flash memory has evolved from the single-level cell and multi-level cell into the triple-level cell (TLC). NAND flash memory has physical problems such as the characteristic of erase-before-write and the limitation of program/erase cycles. Moreover, TLC NAND flash memory has low reliability and short lifetime. Thus, we propose a dynamic Huffman coding method that can apply to the write operations of NAND flash memory. The proposed method exploits observations from a Huffman tree and machine learning from data patterns to dynamically select a suitable Huffman coding. According to the experimental results, the proposed method can improve the reliability of TLC NAND flash memory and also consider the compression performance for those applications that require the Huffman coding.

We propose to use overlapped and adaptive Gaussian smoothing (OAGS) and convolutional refinement networks (CRN) to recover images corrupted by salt-and-pepper noise. First, the OAGS method identifies noise pixels and recover them. Then, CRN further improve and restore the recovered results with sharper and clearer edges. Experimental results demonstrate the proposed OAGS+CRN method significantly outperforms state-of-the-art denoising methods.

In the storage systems of NAND flash memory, an intermediate software called a Flash Translation Layer (FTL) is adopted to hide the characteristics of NAND flash memory and provide efficient management for NAND flash memory. Current flash translation layers can be classified into a page-mapping FTL, a block-mapping FTL, and a hybrid-mapping FTL. In order to utilize the advantages of the page-mapping FTL and the block-mapping FTL, the hybrid-mapping FTL is proposed to store data to the appropriate mapping mechanism by switching the mapping information between the page-mapping mechanism and the block-mapping mechanism. In the article, we propose a joint operation mechanism to rethink the advantages of the page-mapping FTL, the block-mapping FTL, and the hybrid-mapping FTL. With the joint operation mechanism, a flash translation layer can consider the main memory requirements, improve the system performance, and reduce the garbage collection overhead. The experimental results show that the proposed joint operation mechanism can achieve the goal under realistic workloads and benchmarks.

Flash memory has been widely utilized in embedded systems and consumer electronics, because of its low-power consumption, high-performance access, non-volatility, and shock resistance. A flash-memory device is different from a typical hard-disk device and requires a sophisticated management method to improve the reliable endurance and provide the efficient storage management. To improve the reliable endurance and provide the efficient storage management, the previous works have demonstrated that the identification of the frequently used data and the least recently used data is a key point. In this paper, we will propose a hotness filter of files to calculate how the files are accessed (i.e., reads and writes) intensively. The proposed filter is designed specifically to distinguish between hot and cold files by considering the characteristics of non-volatile memory systems and Android systems. In the experiments, we have implemented the hotness filter in a real Android system (e.g., Asus Nexus 7) and demonstrated that the proposed filter can correctly identify hot and cold files without significant overhead.

Because flash memory now provides an economical solution for various portable devices and embedded systems, an NAND flash-based storage system has replaced the hard disk drive in many applications. Recently, the implementation of database systems using an NAND flash-based storage system has become an important research topic. In particular, the external sorting is an important operation in database systems. With the very distinctive characteristics of flash memory, the typical external sorting system that adopts a clustered sorting process can result in performance degradation and reduce the reliability of flash memory. In this article, we will propose an unclustered sorting method that considers the unique characteristics of flash memory, and we then propose a decision rule to exploit the advantages of both clustered and unclustered sorting. The decision rule can separate records according to their record length, sort them appropriately by the clustered and unclustered sorting, and merge the sorted results. The experimental results show that the proposed method can improve performance in an NAND flash-based storage system (i.e., solid-state drive).

In recent years, advances in virtualization technology have enabled multiple virtual machines to run on a physical machine, such that each virtual machine can perform independently with its own operating system. The IT industry has adopted virtualization technology because of its ability to improve hardware resource utilization, achieve low-power consumption, support concurrent applications, simplify device management, and reduce maintenance costs. However, because of the hardware limitation of storage devices, the I/O capacity could cause performance bottlenecks. To address the problem, we propose a hybrid storage access framework that exploits solid-state drives (SSDs) to improve the I/O performance in a virtualization environment.

In recent years, virtualization technology enables multiple virtual machines to run on a physical machine, where each virtual machine can run independently and own its operating system. Virtualization technology has been adopted in many IT industries because of its ability to improve hardware resource utilization, achieve low-power consumption, simplify server management, and reduce maintenance cost. However, since the hardware limitation of storage devices, I/O capacity could cause performance bottleneck. In the paper, we will propose a hybrid storage access framework for virtualization environment to dynamically adjust and enhance I/O performance by using solid-state drives (SSDs).

Recently, the capacity of flash-memory storage systems has grown rapidly, and flash-memory technology has advanced along with the wave of consumer electronics and embedded systems. In order to properly manage product cost and initialization performance, vendors face serious challenges in system design and analysis. Thus, the timing analysis of system initialization and crash recovery for a segment-based flash translation layer has become an important research topic. This article focuses on system initialization, crash recovery, and timing analysis. The timing analysis of system initialization involves the relationship between the size of the main memory and the system initialization time. The timing analysis of crash recovery explains the worst case recovery time. The experiments in this study show that the timing analysis of system initialization and crash recovery can be applied to the segment-based flash translation layer.

While the capacity of flash-memory storage systems keeps increasing significantly, an effective and efficient management of flash-memory space has become a critical design issue. Different granularities in space management impose different management costs and mapping efficiency. In this paper, we will explore an address translation mechanism (AddrTM) that can dynamically and adaptively switch between different granularities in the mapping of logical block addresses into physical block addresses in flash-memory management. The objective is to provide high performance in address mapping and space utilization and, at the same time, to have the main memory requirements, the garbage collection overhead, and the system initialization time under proper management. The experimental results show that the proposed adaptive mechanism can provide better performance improvement and practicability than other well-known coarse-grained management mechanisms over realistic workloads.

The capacity of flash memory storage systems has been growing at a speed similar to many other storage systems. In order to properly manage the product cost, vendors face serious challenges in resource-limited embedded systems. In this article, a self-adjusting flash translation layer is proposed with low memory requirements. The objective of the design is to provide efficient address mapping and low garbage collection overhead, while controlling main memory usage of the flash translation layer. The capability of the design is evaluated over realistic workloads and benchmarks. System performance is also guaranteed under low memory requirements.

Flash memory has become a popular non-volatile memory technology and is widely used in mobile electronics devices and consumer applications. A flash-memory device is different from typical hard-disk devices and requires sophisticated management to improve the lifetime and the performance. As a result, when a file system is executed on these flash-memory devices, the endurance problem will be an important issue. This is because flash memory could suffer from access errors due to unevenly erase operations on specific locations. In this paper, we will propose a reliable non-volatile memory system by exploiting file-system characteristics. The proposed method can help quick identification of hot and cold files and evenly distribute erase operations over flash-memory devices.When compared to other methods, the proposed method can provide reliable endurance and a more practical solution according to the experimental results.

Flash memory has become a popular device due to its huge-capacity, low-power consumption, non-volatility, and shock-resistance. A flash-memory storage system has replaced a hard-disk drive in many applications, especially in embedded systems. Recently, the implementation of file systems on flash-memory storage systems has become an important research topic. How to efficiently manage files and handle file accesses becomes an important issue. In this paper, we will propose a low-memory management for log-based file systems on flash memory. The experimental results show that the proposed method can provide reasonable performance under a low-memory environment.

Emerging critical issues for flash-memory storage systems, especially with regard to implementation within many embedded systems, are the programmed I/O nature of data transfers and their energy-efficient nature. We propose an I/O request mechanism in the Memory-Technology-Device (MTD) layer to exploit the programmed I/O-based data transfers for flash-memory storage systems. We propose to revise the waiting function in the Memory-Technology-Device (MTD) layer to relieve the microprocessor from busy-waiting, in order to make more CPU cycles available for other tasks. An energy-efficient mechanism based on the I/O request mechanism is also presented for multi-bank flash-memory storage systems, which particularly focuses on switching the power state of each flash-memory bank. We demonstrate that the energy-efficient I/O request mechanism not only saves more CPU cycles to execute other tasks, but also reduces the energy consumption of flash-memory, based on experiments incorporating realistic system workloads.

The capacity of flash-memory storage systems grows at a speed similar to many other storage systems. In order to properly manage the product cost, vendors face serious challenges in system designs. In this paper, an efficient flash translation layer is proposed with low memory requirements. The objective of the design is to provide efficient address mapping with low garbage collection overhead, provided that memory space requirement for the flash translation layer is properly managed. The capability of the design is evaluated over realistic workloads.

With the significant growth of the markets for consumer electronics and various embedded systems, flash memory is now an economic solution for storage systems design. Because index structures require intensively fine-grained updates/modifications, block-oriented access over flash memory could introduce a significant number of redundant writes. This might not only severely degrade the overall performance, but also damage the reliability of flash memory. In this paper, we propose a very different approach, which can efficiently handle fine-grained updates/modifications caused by B-tree index access over flash memory. The implementation is done directly over the flash translation layer (FTL); hence, no modifications to existing application systems are needed. We demonstrate that when index structures are adopted over flash memory, the proposed methodology can significantly improve the system performance and, at the same time, reduce both the overhead of flash-memory management and the energy dissipation. The average response time of record insertions and deletions was also significantly reduced.

While the capacity of flash-memory storage systems keeps increasing significantly, effective and efficient management of flash-memory space has become a critical design issue! Different granularities in space management impose different management costs and mapping efficiency. In this paper, we explore an address translation mechanism that can dynamically and adaptively switch between two granularities in the mapping of logical block addresses into physical block addresses in flash memory management. The objective is to provide good performance in address mapping and space utilization and, at the same time, to have the memory space requirements, and the garbage collection overhead under proper management. The experimental results show that the proposed adaptive mechanism could provide significant performance improvement over the well-known coarsegrained management mechanism NFTL (NAND Flash Translation Layer) over realistic workloads.

While flash memory has been widely adopted for various embedded systems, space efficiency with reasonable performance has become a critical issue for the design of the flash-memory translation layer. The target of this paper is to improve the performance of existing designs by proposing a search-tree-like caching mechanism for efficient address translation. A replacement strategy with a low time complexity is presented to monitor the access status of recently used LBA's. The proposed caching mechanism and replacement strategy were shown being highly effective in the reducing of the address translation time over popular translation layer designs, such as NAND, where realistic workloads were used for experiments.

While flash memory has been widely adopted for storage systems for various embedded systems, issues of performance and reliability have started receiving growing attention in recent years. How to provide efficient roll back and quick mounting for flash-memory file systems has become an important research topic in recent years, in addition to the work on effective garbage collection and superb runtime performance. Such an observation motivates our work on the investigation of efficient initialization and crash recovery of flash-memory file systems based on log structures. A methodology is proposed for the acceleration of mounting and crash recovery for log-based file systems. A system prototype based on a well-known flash-memory file system, YAFFS, was implemented with performance evaluation. Experimental results show that the proposed methodology can reduce mounting time significantly, regardless of whether the file system is properly unmounted.

For many applications with spatial data management such as Geographic Information Systems (GIS), block-oriented access over flash memory could introduce a significant number of node updates. Such node updates could result in a large number of out-place updates and garbage collection over flash memory and damage its reliability. In this paper, we propose a very different approach which could efficiently handle fine-grained updates due to R-tree index access of spatial data over flash memory. The implementation is done directly over the flash translation layer (FTL) without any modifications to existing application systems. The feasibility of the proposed methodology is demonstrated with significant improvement on system performance, overheads on flash-memory management, and energy dissipation.