Approximate computing is an emerging design paradigm for error-tolerant applications, such as multimedia processing and neural network acceleration, which enables significant reductions in circuit area, delay, or power consumption through controlled accuracy trade-offs. This paper presents a novel deep reinforcement learning (DRL)-based framework for approximate logic synthesis (ALS) augmented with a backtracking mechanism, aimed at minimizing the area–delay product (ADP) while satisfying error rate constraints. The experimental results demonstrate that our approach can reduce the ADP by up to 92.83%, and 56.79% on average under a 5% error rate constraint.

This paper presents a 3-Level Buck Converter (3LBC) with a Fast-Flying Capacitor Charging (FFCC) technique. Unlike previous Flying Capacitor voltage (VCF) calibration methods, FFCC allows VCF to track input voltage (VIN) changes even without switching events. This continuous calibration keeps VCF close to VIN/2 and eliminates over-voltage stress during sudden VIN shifts. Additionally, FFCC enables faster calibration compared to previous methods, which were limited by the loop bandwidth due to stability concerns. FFCC, using only a comparator, achieves higher speed without stability issues. Experimental results show that with FFCC enabled, VCF stabilizes within 10µsec when VIN changes from 2.8V to 5V, compared to 3msec without FFCC. The steady-state VCF deviation remains within 1.7% of VIN/2, demonstrating FFCC's effectiveness under both transient and steady-state conditions. The proposed 3LBC achieves over 85% efficiency across a 1mA to 500mA load range, with a peak efficiency of 94.8%. The chip, fabricated in a 180nm CMOS process, occupies an area of 2.7mm x 1.7mm.

Low latency and high throughput are critical to enhance immersive Extended Reality (XR) experiences. To overcome the limitations of XR devices’ battery and antenna constraints, we investigate a relay-assisted carrier aggregation (RACA) system that transmits data across two frequency bands. However, the iterative weighted minimum mean square error (WMMSE) algorithm used for maximizing data rate incurs long latency. To address this, we propose a deep unfolding WMMSE (UWMMSE) with trainable step sizes in each layer to accelerate convergence via gradient descent. Furthermore, we reschedule serial updates into parallel updates, omit a less-sensitive precoder update for balanced computation, and develop hardware-friendly approximations to simplify matrix inversion and square root operations. To satisfy real-time communication, we implement the first dual-mode UWMMSE hardware engine with folding and pipeline techniques that reduces area by 75% compared to direct mapping and supports MU-MIMO precoder optimization. This engine achieves 1.3x higher hardware efficiency than prior generalized eigenvalue decomposition (GEVD)-based MU-MIMO processors, completing 4 iterations of UWMMSE within 0.4 µs.

Extended Reality (XR) applications demanding high data rates pose significant challenges for uplink transmissions from user equipment (UE) with limited power and antenna resources. Recently, relay-assisted carrier aggregation (RACA) systems have been proposed to enhance data rates by transmitting data across two frequency bands. This paper addresses the practical issues of power-constrained XR devices and imperfect channel state information (CSI) in RACA systems. We propose a robust Dinkelbach's-transformed weighted minimum mean square error (DWMMSE) framework to maximize energy efficiency (EE) and minimize mean square error (MSE) under Gaussian CSI errors. The framework adapts to content-intensive, powerconstrained, and reliability-critical XR scenarios through specific alternating optimization settings. Simulation results demonstrate that DWMMSE achieves superior EE with a 92% reduction in complexity compared to baseline methods. Moreover, it delivers lower MSE and bit error rate (BER) than non-robust schemes.

High-mobility communications in 6G systems face challenges due to Doppler shifts that degrade the performance of traditional orthogonal frequency division multiplexing (OFDM). Affine frequency division multiplexing (AFDM) offers high spectral efficiency but requires efficient detection to exploit its diversity gain. We introduce expectation propagation (EP) as an effective detector for AFDM, improving decoding by estimating the joint posterior distribution of symbols. However, EP incurs high complexity due to matrix inversion, and the Neumannseries approximation (NSA), which is widely used to reduce matrix inversion complexity, fails in AFDM systems due to ill-conditioned channel matrices. To address this, we propose a message passing-initialized approximated-variance EP (MPI-AVEP). It exploits the quasi-banded structure of AFDM channel matrices to reduce the total complexity. The MPI-AVEP achieves performance similar to traditional EP while reducing complexity from cubic to linear in the number of subcarriers. Thus, it offers a practical solution for high-mobility communication systems.

In millimeter-wave (mmWave) systems aided by intelligent reflecting surfaces (IRSs), accurate channel estimation under low pilot overhead is challenging because of the large number of passive IRS elements. By exploiting the low-rank nature of mmWave channels in the virtual angular domain (VAD) and the powerful learned approximate message passing (LAMP) network, we propose a two-stage LAMP network with row compression (RCTS-LAMP). Specifically, the two LAMP networks jointly recover the VAD channel by solving two low-dimensional sparse signal recovery problems. Moreover, row compression is adopted between the two networks to further reduce the complexity according to the row sparsity structure. Numerical results show that the estimation performance is increased while the computational complexity can be significantly reduced, which achieves a better trade-off between the accuracy and the complexity.

This paper proposes a ring amplifier with a self-stabilization technique (SST) against PVT variation. It can significantly alleviate the risk of the instability issue, which is particularly problematic in the front-end design. This technique automatically adjusts the dead-zone voltage (${V}_{DZ}$) according to the output voltage ringing magnitude directly. With the technique, the ring amplifier can find a suitable dead-zone voltage with minimal accuracy degradation even in a wide PVT range without adding a complex control circuit or algorithm. This technique is applied on a ring amplifier with 10-bit SAR (Successive-Approximation) ADC, and both are implemented in the 40-nm CMOS process. According to the measurement results, 51.43 dB SNDR, 60.24 dB SFDR, and 8.25-bit at 500ksps are achieved while consuming 36$\mu$W.

Recently, hardware Trojan has become a serious security concern in the integrated circuit (IC) industry. Due to the globalization of semiconductor design and fabrication processes, ICs are highly vulnerable to hardware Trojan insertion by malicious third-party vendors. Therefore, the development of effective hardware Trojan detection techniques is necessary. Testability measures have been proven to be efficient features for Trojan nets classification. However, most of the existing machine-learning-based techniques use supervised learning methods, which involve time-consuming training processes, need to deal with the class imbalance problem, and are not pragmatic in real-world situations. Furthermore, no works have explored the use of anomaly detection for hardware Trojan detection tasks. This paper proposes a semi-supervised hardware Trojan detection method at the gate level using anomaly detection. We ameliorate the existing computation of the Sandia Controllability/Observability Analysis Program (SCOAP) values by considering all types of D flip-flops and adopt semi-supervised anomaly detection techniques to detect Trojan nets. Finally, a novel topology-based location analysis is utilized to improve the detection performance. Testing on 17 Trust-Hub Trojan benchmarks, the proposed method achieves an overall 99.47% true positive rate (TPR), 99.99% true negative rate (TNR), and 99.99% accuracy.

T-DNA activation-tagging technology is widely used to study rice gene functions. When T-DNA inserts into genome, the flanking gene expression may be altered using CaMV 35S enhancer, but the affected genes still need to be validated by biological experiment. We have developed the EAT-Rice platform to predict the flanking gene expression of T-DNA insertion site in rice mutants. The three kinds of DNA sequences including UPS1K, DISTANCE, and MIDDLE were retrieved to encode and build a forecast model of two-layer machine learning. In the first-layer models, the features nucleotide context (N-gram), cis-regulatory elements (Motif), nucleotide physicochemical properties (NPC), and CG-island (CGI) were used to build SVM models by analysing the concealed information embedded within the three kinds of sequences. Logistic regression was used to estimate the probability of gene activation which as feature-encoding weighting within first-layer model. In the second-layer models, the NaiveBayesUpdateable algorithm was used to integrate these first layer-models, and the system performance was 88.33% on 5-fold cross-validation, and 79.17% on independent-testing finally. In the three kinds of sequences, the model constructed by Middle had the best contribution to the system for identifying the activated genes. The EAT-Rice system provided better performance and gene expression prediction at further distances when compared to the TRIM database. An online server based on EAT-rice is available at http://predictor.nchu.edu.tw/EAT-Rice.

The non-isolated buck topology for LED driver is proposed to reduce volume and cost without the need of large transformer. Besides, in the entire universal range of AC input voltage, the proposed self-adjusted feed-forward control (SAFFC) technique ensures small variation in the LED current. The auto-tracking off-time control (ATOTC) technique is also adopted to adjust the off time to guarantee the current accuracy is better than that of the peak current control (PCC) technique while and the efficiency is better than that of the hysteresis current control (HCC) technique. Test chip fabricated in VIS 0.5μm 700V ultra-high voltage (UHV) process demonstrates power factor higher than 0.97, averaged 95% high accuracy, and 95% high efficiency.

BACKGROUND: Mutation of a single amino acid residue can cause changes in a protein, which could then lead to a loss of protein function. Predicting the protein stability changes can provide several possible candidates for the novel protein designing. Although many prediction tools are available, the conflicting prediction results from different tools could cause confusion to users. RESULTS: We proposed an integrated predictor, iStable, with grid computing architecture constructed by using sequence information and prediction results from different element predictors. In the learning model, several machine learning methods were evaluated and adopted the support vector machine as an integrator, while not just choosing the majority answer given by element predictors. Furthermore, the role of the sequence information played was analyzed in our model, and an 11-window size was determined. On the other hand, iStable is available with two different input types: structural and sequential. After training and cross-validation, iStable has better performance than all of the element predictors on several datasets. Under different classifications and conditions for validation, this study has also shown better overall performance in different types of secondary structures, relative solvent accessibility circumstances, protein memberships in different superfamilies, and experimental conditions. CONCLUSIONS: The trained and validated version of iStable provides an accurate approach for prediction of protein stability changes. iStable is freely available online at: http://predictor.nchu.edu.tw/iStable.

Visual communication over wireless channels is becoming important in multimedia. Because of the limited bandwidth and high error rates of the wireless channel, the video codec should be designed to have high coding efficiency in maintaining acceptable visual quality at low bit rates and robustness to suppress the distortion due to transmission errors. The coding efficiency of a 3D subband video codec is optimized by removing not only the redundancy due to spatial and temporal correlation but also perceptually insignificant components from video signals. Unequal error protection is applied to the source code bits of different perceptual importance. An error concealment method is employed to hide the distortion due to erroneous transmission of perceptually important signals. The evaluation of each signal's perceptual importance is made first from measuring the just-noticeable distortion (JND) profile as the perceptual redundancy inherent in video signals, and then from allocating JND energy to signals of different subbands according to the sensitivity of human visual responses to spatio-temporal frequencies. Simulation results show that acceptable visual quality can be maintained in transmitting video sequences with low bit rates (<64 kbps) over the wireless channel of high error rates (up to BER=10/sup -2/), and the distortion due to erroneous transmission of coded data can be effectively suppressed. In the simulation, the noisy channel is assumed to be corrupted by the random errors depending on the average strength of the received wave and the burst errors due to Rayleigh fading.