In this paper, we propose an efficient timing-driven global router, TIGER, for gate array and standard cell layout design. Unlike other conventional global routing techniques, interconnection delays are modeled and included during the routing and rerouting process in order to minimize the maximum channel density for gate arrays or the total track number for standard cells, as well as to satisfy the timing constraints in TIGER. The timing-driven global routing problem is formulated as a multiterminal, multicommodity network flow problem with integer flows under additional timing constraints. Two novel performance-driven Steiner tree algorithms are proposed to generate the initial global routing trees. A critical-path-based timing analysis method is used to guarantee the satisfaction of timing constraints. Experimental results based on MCNC (ISCAS) benchmarks show that TIGER can obtain better results than or comparable results with TimberWolf 5.6.

For the generation of a risk-free layout solution of a chip, crosstalk synthesis should be pursued at various stages in the routing process. This paper proposes a post global routing crosstalk optimization approach, which to our knowledge, is the first to estimate and reduce crosstalk risk at the global routing level. It consists of two parts: region-based crosstalk risk estimation and crosstalk risk reduction at the global routing level. In the first part, crosstalk risk graphs are first introduced for each routing region representing its current crosstalk situation. The crosstalk risk of each region, which indicates whether a risk-free routing solution of the region is possible, is then quantitatively defined and estimated using a graph-based approach. In the second part, the risk tolerance bound of each net is partitioned appropriately among its routing regions via integer linear programming for accurate (minimized) crosstalk risk estimation. If high risk regions still exist after bound partitioning, net ripping-up and rerouting is applied to reduce their crosstalk risks. At the end of the entire optimization process, a risk-free global routing solution is obtained together with partitions of nets' risk tolerance bounds which reflect the current crosstalk situation of the chip. These can greatly facilitate the generation of a risk-free final solution at later stages in the layout process. The proposed approach has been implemented and tested on CBL/NCSU benchmarks and the experimental results are very promising.

Previous approaches for crosstalk synthesis often fail to achieve satisfactory results due to limited routing flexibility. Furthermore, the risk tolerance bounds partitioning problem critical for constrained optimization has not been adequately addressed. This paper presents the first approach for crosstalk risk estimation and reduction at the global (instead of detailed) routing level. It quantitatively defines and estimates the risk of each routing region using a graph-based optimization approach and globally adjusts routes of nets for risk reduction. At the end of the entire optimization process, a risk-free global routing solution is obtained together with partitions of nets' risk tolerance bounds which reflect the crosstalk situation of the chip. The proposed approach has been implemented and tested on CBL/NCSU benchmarks and the experimental results are very promising.

In this paper, we present new moment models for uniform, nonuniform and coupled transmission lines. The moment model of a line is based on the relationships between the two port currents (KCL) and the two port voltages (KVL) of the line. The parameters of the model depend on the mean values of the voltage moments and the weighted voltage moments of the line. Simple formulas are given to compute these mean values efficiently. By using such models and moment matching techniques, interconnects modeled as transmission line networks can be efficiently simulated. In addition, by using moment sensitivities, we demonstrate that wire sizing optimization can be carried out for layout design.

Most existing performance-driven and clock routing algorithms construct optimal routing topology for each net individually without considering its routability on the chip, so they can not guarantee performance after all nets are routed. This paper proposes a new approach for post routing performance optimization via multi-link insertion and non-uniform wiresizing, which improves the performance of a net topology obtained from a global routing solution. Unlike previous approaches, it can achieve reduction in both maximum delay and skew to satisfy user specified constraints and minimizes the routing resource consumed. During optimization, the topology of the net is kept routable. Experiments show that link insertion and wiresizing can improve net performance significantly, and among all approaches, multi-link insertion and wiresizing achieves the best performance and area efficiency.

This paper presents two performance-driven Steiner tree algorithms or global routing which consider the