The increasing deployment of neural networks in safety-critical domains, such as autonomous driving and embodied artificial intelligence, has underscored the urgent need for fault-tolerant neural architectures. Hardware-induced faults stemming from soft errors, aging, or other disturbances can severely impair model performance. In this paper, we propose a hierarchical optimization framework that systematically designs fault-tolerant neural architectures from operator design to architecture search method, while minimizing both accuracy loss and computational cost. Specifically, we design a fully decoupled Winograd convolution operator (FD-WGC) that localizes the impact of bit-flip faults and reduces computational cost. We then expand the architecture search space by introducing fault-tolerant cells composed of the FD-WGC and complementary operators, enabling more flexible network construction. Within this expanded search space, we employ MOBO-NAS, a multi-objective Bayesian optimization based neural architecture search method, to efficiently explore neural architectures that balance accuracy, computational cost, and fault tolerance. Experimental results show that our framework enhances fault tolerance by up to 510× compared to state-of-the-art (SOTA) manually designed and automatically searched architectures, while maintaining comparable accuracy and reducing computational cost by up to 80%. Extensive evaluations across diverse hardware fault models further validate the generalizability and effectiveness of our proposed framework. All codes are available at https://github.com/cc-innocence/MOBO-NAS/tree/master.

Static random access memory (SRAM) plays a critical role in chips due to its high-speed access capabilities, but it suffers from data loss upon power-down and is susceptible to radiation-induced faults. Nonvolatile SRAM (NVSRAM) has attracted substantial research attention for combining the high-speed operation of SRAM with the nonvolatile storage capabilities of emerging memory technologies. This article proposes a 12T2R NVSRAM cell based on resistive random access memory (RRAM), achieving nanosecond-scale data backup and recovery. The novel design integrates an independent RRAM operation path and an SRAM power-gating switch, ensuring reliable backup and low-power sleep mode. Building on the memory array, the system further integrates a power management module, control and driver circuitry, and a dual-layer error correction code (ECC) strategy. This holistic co-design across device, circuit, and architecture levels delivers enhanced reliability, energy efficiency, and fault tolerance. Simulation results under 65 nm CMOS process demonstrate significant improvements in key performance metrics, including speed, power consumption, noise margin, store/restore yield, and bit error rate (BER). All functional modules meet the design specifications, with markedly improved data backup and restoration success rates, providing a promising solution for next-generation high-performance nonvolatile memory (NVM) systems.

As integrated circuits (ICs) continue to scale, soft errors pose a growing threat to system reliability—particularly in safety-critical applications. Among various circuit components, flip-flops (FFs) are especially susceptible to soft errors due to their state-holding nature, making them prime targets for selective hardening. However, such hardening introduces area and power overheads, necessitating careful tradeoffs. Existing methods typically rely on multiobjective optimization (MOO) algorithms to identify Pareto-optimal hardening strategies, yet their inherent randomness limits controllability, and they must be rerun entirely for each new circuit instance, resulting in poor adaptability. In this work, we propose a deep reinforcement learning (DRL)-based hardening optimizer that supports zero-shot generalization to unseen circuits. Built upon the advantage actor–critic (A2C) framework, our model is trained on synthetic circuits and learns to make sequential hardening decisions under strict resource constraints. A recurrent neural network (RNN) captures the historical context of prior hardening steps, while an attention mechanism dynamically focuses on FFs with high soft-error vulnerability at each decision step. Experimental evaluations on benchmark circuits demonstrate that our proposed framework achieves an average hypervolume (HV) improvement of 19.58%. Furthermore, the framework provides at least a$9.9\times $runtime speedup for individual circuits, offering an agile and generalizable solution for reliability-centric circuit design. The source code is available athttps://github.com/Magic00JuJu/ZACHO/tree/main

The ever-expanding scale of integrated circuits has brought about a significant rise in the design risks associated with radiation-resistant integrated circuit chips. Traditional single-particle experimental methods, with their iterative design approach, are increasingly ill-suited for the challenges posed by large-scale integrated circuits. In response, this article introduces a novel sensitivity-aware single-particle radiation effects simulation framework tailored for System-on-Chip platforms. Based on SVM algorithm we have implemented fast finding and classification of sensitive circuit nodes. Additionally, the methodology automates soft error analysis across the entire software stack. The study includes practical experiments focusing on RISC-V architecture, encompassing core components, buses, and memory systems. It culminates in the establishment of databases for Single Event Upsets (SEU) and Single Event Transients (SET), showcasing the practical efficacy of the proposed methodology in addressing radiation-induced challenges at the scale of contemporary integrated circuits. Experimental results have shown up to 12.78× speed-up on the basis of achieving 94.58% accuracy.

Conventional hardened cells are not robust enough to single event upset (SEU) in 28nm technology due to the scaling of the transistors. High soft error rate is caused by particle striking at cells and logic circuit in SRAM. This work proposes an SEU robust dual access 12T (DA-12T) SRAM with a radiation hardened crossbar-based peripheral circuit (CBPC). The proposed cell with 209% area penalty is more SEU robust than most cells. The CBPC can reduce the read failure rate of SRAMs. The new sense amplifier ensures the correct and rapid reading operation speed when suffering read disturbance. The experiment results show that the SEU cross-section of proposed cell is 60% of standard cell with dummy. Almost no read failure is observed in SRAM with CPBC when operational frequency exceeds 40MHz. Further investigation indicated that DA-12T cell and well isolation technique can reduce the read failure rate.