EDBT 2026 Demo / reviewers in the wild / expert
Thomas J. Brosnan
dblp:56/4503
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 2001
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware reliability and fault tolerance · 83% Embedded and real-time systems · 8% Integrated circuit design · 8% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware reliability and fault tolerance
arithmetic codes |
0.0 | 1 | 1988 | Modular Error Detection for Bit-Serial Multiplication · IEEE Trans. Computers 1988 |
Hardware reliability and fault tolerance
error detection |
0.0 | 1 | 1988 | Modular Error Detection for Bit-Serial Multiplication · IEEE Trans. Computers 1988 |
Hardware reliability and fault tolerance › arithmetic codes
residue codes |
0.0 | 1 | 1988 | Modular Error Detection for Bit-Serial Multiplication · IEEE Trans. Computers 1988 |
Integrated circuit design › digital circuit design › arithmetic circuit design › multiplier design
bit-sequential multiplier |
0.0 | 1 | 1988 | Modular Error Detection for Bit-Serial Multiplication · IEEE Trans. Computers 1988 |
Embedded and real-time systems › embedded processor
digital signal processor architecture |
0.0 | 1 | 1988 | Modular Error Detection for Bit-Serial Multiplication · IEEE Trans. Computers 1988 |
Methods — techniques the papers use, named apart from their topics
computer simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2001 | Application of Information Technology: BrainImageJ: A Java-based Framework for Interoperability in Neuroscience, with Specific Application to NeuroimagingabstractThe Human Brain Project consortium continues to struggle with effective sharing of tools. To facilitate reuse of its tools, the Stanford Psychiatry Neuroimaging Laboratory (SPNL) has developed BrainImageJ, a new software framework in Java. The framework consists of two components-a set of four programming interfaces and an application front end. The four interfaces define extension pathways for new data models, file loaders and savers, algorithms, and visualization tools. Any Java class that implements one of these interfaces qualifies as a BrainImageJ plug-in-a self-contained tool. After automatically detecting and incorporating new plug-ins, the application front end transparently generates graphical user interfaces that provide access to plug-in functionality. New plug-ins interoperate with existing ones immediately through the front end. BrainImageJ is used at the Stanford Psychiatry Neuroimaging Laboratory to develop image-analysis algorithms and three-dimensional visualization tools. It is the goal of our development group that, once the framework is placed in the public domain, it will serve as an interlaboratory platform for designing, distributing, and using interoperable tools. Yi-Ren Ng, Smadar Shiffman, Thomas J. Brosnan, Jonathan M. Links, Leu S. Beach, Nicholas S. Judge, Yirong Xu, Uma V. Kelkar, Allan L. Reiss |
J. Am. Medical Informatics Assoc. | 3 |
| 1988 | Modular Error Detection for Bit-Serial MultiplicationabstractSpecial-purpose architectures have been proposed to provide high processing rates for signal processing applications. These architectures use highly concurrent structures on VLSI circuits to achieve billions of multiply/add operations per second. Both serial-parallel and fully bit-serial multiplier elements have been proposed for highly concurrent signal processing arrays. Error detection can be accomplished by applying arithmetic codes to the multiplier hardware in different ways. Here, low-cost residue codes are applied to three different error detection architectures for both serial-parallel and fully bit-serial processing elements. The error performance of these different implementations is studied through computer simulation. The cost of using these codes in terms of silicon area and circuit complexity is also investigated.> Thomas J. Brosnan, Noel R. Strader II |
IEEE Trans. Computers | 1 |