Computing-in-memory (CIM) represents a pivotal technology for overcoming the speed and power bottlenecks posed by the “memory wall” and “power wall” existing in von Neumann architectures. With the fast development of Internet of Things, data security has become one of the most attractive research topics for CIM in edge applications, as well as computing accuracy and energy efficiency. This paper proposes a highly accurate and secure MRAM-based CIM macro that is designed to reduce the multiply accumulate (MAC) computation errors and protect weight bits in untrusted environments. The architecture employs a series-connected structure to enhance computational linearity and introduces a dynamic reference column to increase reliability. Meanwhile, a lightweight encryption mechanism based on physical unclonable function (PUF) is implemented to protect weight bits. The results demonstrate that, after the obfuscation, the prediction accuracy of machine learning-based attacks on the PUF is reduced to approximately 50%. The CIM macro achieves impressive inference accuracy of 93.73% on the CIFAR-10 dataset with energy efficiency of 38.3 TOPS/W. Furthermore, security verification performed on the CNN model indicates that weight encryption degrades inference accuracy to 10%, thereby providing robust protection against potential attacks.

With the rapid advancement of space exploration technology, the use of intelligent equipment and systems is increasing at an accelerated pace. As the core component of intelligent systems, integrated circuits (ICs) have become a key area of research in space applications. However, the complex space environment significantly degrades the reliability of ICs due to radiation effects. As a result, radiation hardening technology is critical for ICs used in space applications. Unlike general consumer electronics, students majoring in ICs are often unfamiliar with radiation hardening technologies, which is a disadvantage for those who may work in industries such as aerospace, nuclear, or medical electronics after graduation. This paper explores teaching methods for a course on radiation hardening technology in ICs. Through interdisciplinary collaboration and joint university-enterprise teaching, as well as classroom interaction and project-based learning, students will gain an in-depth understanding of radiation sources, radiation effects, hardening techniques, and irradiation testing.

Although magnetic tunnel junction (MTJ) is intrinsically immune to radiation, non-volatile ternary content-addressable memory (NV-TCAM) cells are still susceptible to single event upset (SEU). This results in erroneous search results. In this paper, we propose a radiation-hardened non-volatile ternary content-addressable memory (RH-TCAM) cell based on spin transfer torque magnetic tunnel junction (STT-MTJ) to address the impact of SEU. In order to demonstrate its functionality, hybrid simulations have been performed by using a STT-MTJ compact model and the CMOS 28 nm design kit. Simulation results show that the proposed RH-TCAM can fully tolerate SEU when the amount of the deposited charge (Qinj) reaches up to 2 pC.

The rapid development of Internet of Things (IoT) devices has triggered massive data transmission. Meanwhile, advances in artificial intelligence (AI) introduce new security vulnerabilities in device interactions. These challenges demand lightweight yet robust security solutions. In this context, physical unclonable functions (PUFs) serve as critical hardware security primitives, enabling reliable authentication for edge devices. Nevertheless, PUF is increasingly susceptible to novel threats, notably machine learning attacks. To address this security vulnerability to attacks, we propose a novel double-layer dynamic challenge cross-selection magnetoresistive random access memory PUF (MPUF). This design leverages the inherent process variation in spin-transfer torque magnetoresistive random access memory (STT-MRAM) as an entropy source. The proposed structure incorporates an obfuscation decode circuit (ODC) that combinesxorgates and shift registers. It dynamically obfuscates interlayer relationships between two PUF arrays to enhance circuit nonlinearity. The simulation results demonstrate uniformity of 50.16%, uniqueness of 49.94%, a worst bit error rate (BER) of 2.34% for$- 25~^{\circ } $C to$125~^{\circ } $C and 1.56% for$0.5\sim 1.1$V. In addition, four common machine learning models are used to attack this PUF, achieving accuracies of 50.49%, 50.49%, 50.48%, and 58.41%, which are close to a random guess. Compared with traditional PUF implementations, this work exhibits higher reliability and enhanced security while maintaining low power consumption of approximately 9.975 fJ/bit.

This paper presents a novel compute-in-memory (CIM) macro, which mainly consists of three modules: input generator, 9T1C-SRAM CIM array and charge-integration-count output (CICO) circuit. For the input generator, it can achieve the pulse-width modulation mapping scheme without counts, leading to a small area overhead. For the CIM array, one row-cascade current mirror circuit instead of a bias voltage source is shared by all CIM cells in one row. And in each CIM cell, its multiply result is characterized by the charge on its capacitor. Based on the charge-sharing principle, the accumulated result is represented by the charge ($\text{Q}_{\text {CBL}}$) on the charge-bit-line (CBL). In this way, the voltage on the CBL is limited regardless of the number of rows of the CIM array, allowing the large-scale CIM array. For the CICO circuit, it is proposed to quantify the$\text{Q}_{\text {CBL}}$without the ADC, aiming to achieve high area efficiency. With the 14nm FinFET design kit, the design specification of the proposed CIM macro is introduced in detail and its performance is evaluated. Simulation results show that the proposed CIM macro can achieve 4–1370 TOPS/W energy efficiency with IN/W/OUT precision of 6/1/6b and 98.48%/84.56% test accuracy on MNIST and CIFAR-10.

In this paper, we present a reconfigurable Physically Unclonable Functions (PUF) based on the Spin-Orbit-Torque Magnetic Random-Access Memory (SOT-MRAM), which exploits thermal noise as the true dynamic entropy source. Therefore, the MRAM cells could be configured to random final states with stochastic switching mechanism. The proposed PUF is constructed and reconfigured by combining the small-capacity true random number generator (TRNG) and high-reliability secure hash algorithm (SHA-512), realizing the dynamic transformation between SOT-MRAM based last level cache and PUF (In-Cache-MPUF). Thanks to the full reconfigurability and the high endurance of SOT-MRAM, the proposed In-Cache-MPUF can achieve$10^{\textbf {14}}$maximum PUF bits per cell, which has greatly motivated the implementations compared with the traditional weak PUFs utilizing the static entropy source of process variations. The Monte-Carlo simulation results using 40 nm technology and a compact MTJ model show that the proposed PUF has desirable randomness as the digitized bit streams passing all the NIST tests, achieving 50.0428% uniqueness as well as 49.9236% uniformity. It also shows comparable reliability to the state-of-the-art works: a maximum bit error rate of 0.14% and 0.12% at 100 °C and 0.9 V, respectively. In addition, the system level performance is tested and validated by gem5.

With the rapid development of the Internet of Things (IoT) infrastructure, electronic devices are becoming ubiquitous, in which authentication and secure communication are required. As a result, novel hardware security primitives have been developed to overcome the deficiencies of conventional security methods and address the growing security issues. Physical unclonable function (PUF) is an emerging hardware security primitive that plays an important role in authenticity and reliability of integrated circuits (ICs). Spin-transfer torque magne- toresistive random access memory (STT-MRAM) is a promising technology that is dense, fast, non-volatile, highly endurant and energy-efficient. STT-MRAM is considered a promising primitive as it has several intrinsic randomness sources, such as stochastic switching, process variations and statistical read/write failures. This paper proposes a novel hybrid STT-MRAM/complementary metal-oxide semiconductor (CMOS) based reconfigurable arbiter PUF. The functionality of the design is validated by a 28nm CMOS technology and a compact magnetic tunnel junction (MTJ) model. Simulation results show that the proposed PUF has a mean intra-hamming distance (HD) of 0.24%, a mean inter-HD of 51.1% and passes the National Institute of Standards and Technology (NIST) statistical tests.

Flip-flops (FFs) are basic units in electronic circuits. Recently, nonvolatile FFs (NVFFs) have attracted great interests for power-gating applications and a variety of NVFFs have been proposed by integrating nonvolatile memory devices. Among them, magnetic tunnel junction (MTJ) based NVFFs show considerable potential in terms of zero static power consumption and high endurance. Nevertheless, the mainstream spin transfer torque (STT) effect based MTJ switching approach for data storing still consumes much dynamic power and long delay, limiting the system performance and data reliability. The spin-orbit torque (SOT) effect provides an alternative approach for high-speed and low-power MTJ switching, therefore rather promising for NVFF design. In this work, we propose four NVFF designs based on the FF architectures (either DFF or SRFF) and perpendicular MTJ (pMTJ). The circuit structures and operations are investigated, and the performance is evaluated and compared at the 40 nm process technology node. Simulation results show that the proposed NVFFs can achieve high read speed (<; 200 ps), low read power consumption (<; 10 fJ) and area efficiency.

With low power consumption, fast access speed, high scalability and infinite endurance, spin-transfer torque magnetoresistive random access memory (STT-MRAM) is considered as one of the most promising alternatives to SRAM. However, The performance of STT-MRAM is significantly influenced by several reliability issues, such as process variations and stochastic switching. Most of the reliability analysis of relative circuits are performed at bit-cell and memory level, while that at computer-system level is missing. This paper proposes an efficient framework for performance evaluation of STT-MRAM on computer architecture-level implemented by GEM5+NVMain co-simulator in consideration of the reliability issues. The results show that the overall average latency and energy of STT-MRAM can be up to 5.996% and 20.65% larger than that of the nominal cases in a computer system-level memory architecture taking reliability issues into account. Because reliability issues are considered during the design phase, our framework can provide more accurate performance evaluation and contribute to a higher yield of STT-MRAM based computer systems.

Benefitting from its non-volatility, high speed, low power and inherent radiation hardened characteristic, magnetic random access memory (MRAM) has been used in aerospace and avionic electronics. Owing to its high sensing reliability, precharge differential sense amplifier (PCDSA) has been proposed and widely used in MRAM products. However, such PCDSA is based on the conventional CMOS technology and its sensing result is prone to be affected by the single event upset (SEU) and even the single event double node upset (SEDU) when the CMOS technology node shrinks into the nanometer scale. In this paper, we propose a novel PCDSA to tolerate the SEDU, in which the special three-input C-element that behaves as an inverter when its inputs have the same logic value and holds its previous value when its inputs have the different logic values is employed. By using a physics-based STT-MTJ compact model and a commercial CMOS 40 nm design kit, hybrid simulations have been performed to demonstrate its functionality and evaluate its performance. Simulation results show that it can fully tolerate the SEDU when the amount of the deposited charge (Qinj) reaches up to 2 pC. In the worst case where the Qinjis 2 pC, it can achieve a small recover time of 1.3368 ns and low recover energy dissipation of 1.967 pJ with the optimized VDDof 1 V.

Physical unclonable function (PUF) is considered as a promising hardware security primitive for a variety of applications. Recently, with the rapid development of integrated circuit (IC), the requirement for low complexity, high power efficiency and high performance PUFs become urgent. Moreover, a variety of powerful attack approaches have been carried out to counterfeit PUFs. This paper proposes a novel PUF design by utilizing the spin transfer torque magnetic random-access memory (STT-MRAM). The intrinsic process variation of STT-MRAM is exploited as an entropy source for generating PUF response. The primary performance metrics in terms of reliability, uniformity, uniqueness, and diffuseness of our proposed PUF have been verified, which validate its functionality. In addition, machine learning based modeling attacks are employed to evaluate the security level of proposed STT-MRAM based PUF (MPUF). The statistical results show that MPUF is much more immune to modeling attacks compared with the traditional Arbiter PUF.

Voltage-controlled magnetic anisotropy (VCMA)-magnetic tunnel junction (MTJ) is incorporated into FD-SOI CMOS technology. The design space of 1 transistor-1 MTJ (1T-1M) bit-cell is explored through varied VCMA pulse duration/amplitude and scaling down transistor dimensions. The design point with 1.1 V VCMA pulse amplitude, 0.44 ns pulse duration and W/L = 400 nm/30 nm access transistor shows the ultra low write energy in VCMA-MTJ based bit-cell. It achieves a minimum 3.18 fJ/bit switching energy with 28-nm FD-SOI process. Access transistor sizing is studied, while the ultra low power implementation may lead to MTJ switching failure. Voltage assisted techniques for failure mitigation are proposed based on body-bias generator (BBG). The BBG not only provides VCMA pulse signal to control MTJ barrier, but also generates body-bias to boost the transistor performance. In the presence of forward body-bias (FBB) and increased VCMA pulse level, the proposed strategy is effective in switching failure compensation as well as writing delay improvement.

Magnetic tunnel junction (MTJ) is considered as a promising memory candidate in the more than Moore era because of high power efficiency, fast access speed, nearly infinite endurance and easy 3D integration. The nondeterministic switching behavior has been profited to exploit new directions for computing methods, such as stochastic computing. In this paper, the application of stochastic switching behavior in stochastic computing is explored for deep neural network (DNN). Stochastic computing method features low logic complexity, low energy consumption and fine-grained parallelism, boosting the performance of DNN system by combining MTJ. As a key block of stochastic computing, MTJ based true random number generator design is presented in details. The functionality has been validated by combining the hardware design and post-processing in software. Simulation results are demonstrated visibly by handwritten digits recognition test to show the accuracy. Furthermore, the performance is investigated in terms of accuracy, energy consumption and memory occupation to find more efficient techniques.

Reliability concerns arise in nonvolatile magnetoelectric random access memory (MeRAM) due to continuously nanotechnology scaling down and CMOS-magnetic hybrid integration. The primary objective of this work is to investigate failure mitigation in voltage-controlled magnetic anisotropy-magnetic tunnel junction (VCMA-MTJ) based 1T-1MTJ MeRAM bit-cell, by using MTJ compact model and 28nm fully depleted silicon on insulator (FD-SOI) process design-kit. A comprehensive reliability study is performed considering process variation and aging degradations, including hot carrier injection (HCI), bias temperature instability (BTI), soft breakdown (SBD) and radiation effect. Write assist techniques are proposed to ensure failure resilient MeRAM design. Bit line (BL) boost and negative source line (SL) methods show high efficiency in writing latency improvement and failure mitigation.

The energy scalability of ultra-low power nonvolatile (NV) large-scale integration (LSI) is explored in this paper. Multi-threshold computing (super/near/sub-$V_t$) in hybrid CMOS/ magnetic tunnel junction (MTJ) circuits are investigated based on SPICE-compatible MTJ model and fully depleted silicon on insulator (FD-SOI) devices. Ultra-low supply voltage operation bottlenecks associated with performance loss, parametric variations and function failure are studied in differential pair-based sensing circuit, MTJ writing/control circuit and other building blocks. A case study is performed with three typical NV-flip-flops (NV-FF), which are implemented with 28nm FD-SOI low $V_t$ (LVT) device and forward back-bias. Results show that MTJ writing/control circuit must operate at nominal supply (super-$V_t$) region to guarantee MTJ switching; sensing circuit is configured with near-$V_t$ operation (0.6V) with robustness consideration, whereas other parts could be implemented with near/sub-$V_t$ computing to achieve ultra-low power consumption and energy efficient operations.