Heterogeneous photonic-electronic systems, such as co-packaged optics and photonic-electronic artificial intelligence (AI) accelerators, are rapidly gaining traction but also pose significant design challenges due to distinct design methodologies. Digital and analog electronics are typically described using hardware description languages and SPICE, respectively, whereas photonic devices and systems are represented using permittivity tensors on the Yee grid and the Scattering matrix formulation. This disparity necessitates an end-to-end photonic-electronic cosimulation tool to streamline co-design. Most preliminary cosimulation approaches rely on translating photonic compact models into Verilog-A or SPICE models to simulate everything there, which not only introduces the additional complexity of model conversion but also has potential numerical stability problems. Additionally, another critical functionality missing from the current implementation is enabling gradient calculation in these co-simulators, which will be crucial for end-to-end gradient-based electronic-photonic system optimization. To address these challenges, we introduce SPIPE, a differentiable SPICE-level co-simulation framework for integrated photonic-electronic systems. SPIPE is the first co-simulator to overcome model conversion issues and to provide differentiability. Numerical experiments on several circuits confirm the accuracy of SPIPE when compared to analytical solutions and real-world experimental data. Furthermore, in cases where existing simulators are applicable, SPIPE achieves a runtime reduction of 2!+85!A compared to an industry-standard simulator. SPIPE features an integrated simulation interface with a low usage barrier, opening avenues for more accessible and effective photonic-electronic co-design. SPIPE is open sourced: https://github.com/zhengqigao/spipe.

Circuit simulation has developed robust numerical methods to achieve fast DC operating point convergence in highly nonlinear systems. Similar challenges arise in nonconvex optimization, where second-order optimization methods often require restrictive step sizes to ensure a monotonically decreasing objective function. Moreover, in the presence of nonlinear objective functions with large Lipschitz constants, increasingly small step-sizes become a bottleneck to fast convergence. Building on established connections between optimization and circuit dynamics, we explore the application of fast DC circuit simulation methods to second-order optimization. Using a dynamic system representation of the trajectory of optimization variables, we exploit the quiescence of the dynamical system to determine the steady state that coincides with the critical point of the objective function. This optimization via quiescence uses a variation of the quasi-steady state analysis method in ACES to adaptively select large step-sizes that sequentially follow each optimization variable to a quasi-steady state until all state variables reach the actual steady state. The result is a second-order optimization method that utilizes large step-sizes and does not require a monotonically decreasing objective function to reach a critical point. Experimentally, we demonstrate the use of this fast DC circuit simulation for optimizing nonconvex problems in general unconstrained optimization problems including a power systems example and compare them to existing state-of-the-art second-order methods, including damped Newton-Raphson, Broyden–Fletcher–Goldfarb–Shanno (BFGS), and Symmetric Rank 1 (SR1).

In this paper, we leverage a foundational principle of analog electronic circuitry, Kirchhoff's current and voltage laws, to introduce a distinctive class of neural network models termed KirchhoffNet. Essentially, KirchhoffNet is an analog circuit that can function as a neural network, utilizing its initial node voltages as the neural network input and the node voltages at a specific time point as the output. The evolution of node voltages within the specified time is dictated by learnable parameters on the edges connecting nodes. We demonstrate that KirchhoffNet is governed by a set of ordinary differential equations (ODEs), and notably, even in the absence of traditional layers (such as convolution layers), it attains state-of-the-art performances across diverse and complex machine learning tasks. Most importantly, KirchhoffNet can be potentially implemented as a low-power analog integrated circuit, leading to an appealing property --- irrespective of the number of parameters within a KirchhoffNet, its on-chip forward calculation can always be completed within a short time. This characteristic makes KirchhoffNet a promising and fundamental paradigm for implementing large-scale neural networks, opening a new avenue in analog neural networks for AI. Our source code and model checkpoints are publicly available: https://github.com/zhengqigao/kirchhoffnet.

It was originally stated that convolution operations were required to implement adjoint sensitivity in the time domain. In this article, we revisit time-domain adjoint sensitivity with a circuit theoretic approach and an efficient solution is clearly stated in terms of device level. Key is the linearization of the energy storage elements (e.g., capacitance and inductance) and nonlinear memoryless elements (e.g., MOS, BJT DC characteristics) at each time step. Due to the finite precision of computation, numerical errors that accumulate across timesteps can arise in nonlinear elements. A methodology to suppress that error is introduced. Numerical results demonstrate that the proposed method achieves accuracy while significantly reducing computational runtime.

Parametric yield estimation is a critical component in the Integrated Circuit design flow. We propose an efficient non-Monte-Carlo yield estimation method. Key is the use of sensitivity information efficiently obtained with the nominal circuit response. Based on Taylor expansion, the circuit performance can be approximated with a multivariate Gaussian distribution. Combining this with the circuit performance specifications, the yield can be estimated efficiently by repeatedly sampling from the obtained Gaussian distribution. Also proposed is an efficient method to identify impactful factors leading to yield loss (e.g., the most or least sensitive process variables; the tightest performance specifications) based on a multidimensional Venn diagram. Circuit examples demonstrate that the proposed method can well estimate the yield while significantly reducing the number of circuit simulations. Moreover, the proposed yield analysis method can provide useful hints for yield enhancement.

Step-function excitations are convenient abstractions for circuit turn on/off and for switching activities in general. However, they are ill-handled by SPICE-derived circuit simulators that employ implicit integration approximations and substitute steep ramps for steps. An ACES-derived explicit integration method efficiently handles step-functions, manages potential instability, and converges to the steady state. The resulting circuit simulator can be employed to find an initial state size and excursion-limited accuracy control. It also is able to accommodate resistance, capacitance, inductance, and nonlinear elements efficiently and accurately.

A macromodeling technique for digital cells is presented. The proposed macromodel allows fast and accurate signal approximation, as well as delay estimation for CMOS digital circuits. To verify its accuracy, the technique is implemented on different logic gates, a half-adder, and a flip-flop. The simulation results are compared with those obtained with SPICE for a 65-nm CMOS technology with a 1.0-V power supply. The results show the delay offset and amplitude deviation are within 5% of SPICE values for an exponential input with maximum$10^{9}$V/s slope. The execution time of the experimental simulator implemented in MATLAB was more than 1000 times faster than SPICE in all cases.

An electrical and physical synthesis flow for high-speed analog and radio-frequency circuits is presented in this paper. Novel techniques aiming at fast parasitic closure are employed throughout the flow. Parasitic corners generated based on the earlier placement statistics are included for circuit resizing to enable parasitic robust designs. A performance-driven placement with simultaneous fast incremental global routing is proposed to achieve accurate parasitic estimation. Device tuning is utilized during layout to compensate for layout induced performance degradations. This methodology allows sophisticated macromodels of performances versus device variables and parasitics to be used during layout synthesis to make it truly performance-driven. Experimental results of a 4GHz LNA and a mixer demonstrate fast parasitic closure with this methodology.

Despite the fact that more and more electronic design is comprised of analog and mixed signal content, the design flows and methodologies in this area are lagging behind the pace of innovation in digital design. For sure, analog designers are in shorter supply, but this only makes the need for improvements and efficiency that much greater. Only of late have we seen production-worth attempts at functions such as analog synthesis and optimization reach the market. What is needed in today's analog design flow? What are the key technologies that are missing? How does the existing “food chain” need to work together to drive greater efficiencies?

We presen t a new algorithm for computing the capacitance of three-dimensional perfect electrical conductors of complex structures. The new algorithm is significantly faster and uses muc h less memory than previous best algorithms, and is kernel independent.

A hierarchical two-dimensional field solution technique isintroduced for capacitance extraction for VLSI interconnectmodeling. As a basis for compromise between the efficiencyof Boolean rules-based extraction and the accuracy of flatfield solution, this hierarchical approach can handlerealistic conductor cross-sections and multiple conformaland/or planarized dielectrics.

The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper presents a new static switching current estimation algorithm based on the idea of "Expected Current Distributions" (ECDs). Unlike previous "expected waveform" approaches, ECDs model not only the expected value of switching current waveforms over all time, but also the variances and covariances of all waveform segments as well. This extra information allows a switching current waveform to be modeled by a random process with both first and second order ensemble statistics. This specification provides the power spectral density of the switching current and allows the use of traditional frequency domain noise analysis to simulate the behavior of the switching current in the electrical supply network. An ECD simulation procedure is described and results are presented for the ISCAS85 combinational benchmark circuits. Estimated quantities include total average and RMS VDD current, the autocorrelation function of the total VDD current waveform, and per-gate average and RMS VDD currents. The results show speedups of up to 100 x and good agreement with respect to figures obtained using dynamic logic simulation and statistical mean estimation.

In the Fall of 1991, after approximately two years of development, the department of Electrical and Computer Engineering (ECE) at Carnegie Mellon University (CMU) implemented a new curriculum that differed radically from its predecessor. Key features of this curriculum include: Engineering in the Freshman year, a small core of required classes, area requirements in place of most specific course requirements, mandated breadth, depth, design, and coverage across ECE technical areas, a relatively large fraction of free electives, and a single integrated Bachelor of Science degree in Electrical and Computer Engineering. In this paper we review the design of this curriculum, including a taxonomy of problems we needed to address, and a set of general principles we evolved to address them. The new curriculum is described in detail, including new data from an ongoing analysis of its impact on students' curricula choices.>

Adaptively Controlled Explicit Simulation (ACES) is a timing simulation methodology for the verification of the transient behavior of integrated circuits. A new adaptively controlled explicit integration approximation is used that overcomes stability problems encountered in earlier explicit techniques. Circuit partitioning is employed, which allows event driven simulation and exploitation of circuit latency. Piecewise linear models are used for nonlinear devices, allowing efficient simulation of MOS, bipolar, and BiMOS circuits. Simulation accuracy in ACES can be varied by controlling the accuracy of either the integration approximation or the piecewise linear device models. With the combination of generality, exploitation of circuit latency, and ability to vary accuracy effectively, ACES provides an efficient environment for transient simulation of integrated circuits and systems.>

Adaptively Controlled Explicit Simulation (ACES) is a timing simulation methodology for integrated circuits and systems. The paper presents the use of event driven simulation and partitioning to enhance the ACES simulation environment by exploiting the latency present in integrated circuits. ACES also uses an improved, adaptively controlled explicit integration approximation which overcomes the stability problems encountered in earlier explicit techniques. Piecewise linear models are used for nonlinear devices allowing efficient simulation of MOS, BiMOS and bipolar circuits.

The paper describes the modeling and simulation of switched capacitor sigma-delta modulators in AWEswit. AWEswit is a mixed signal simulator for switched capacitor circuits that merges electrical circuit simulation with event driven logic simulation. It employs asymptotic waveform evaluation (AWE) as its core simulation engine. Mixed level modeling of the circuit components is facilitated by AWEswit's ability to combine formulations in the current voltage and charge voltage regimes. AWEswit naturally handles the linear bandwidth limitations associated with switched capacitor circuits. Here, AWEswit's approach to modeling the clock feedthrough and signal dependent charge dump that characterize MOSfet switches is described. In addition, a postprocessing technique to superimpose the effect of component nonlinearity on the linear AWEswit solution is presented.

Adaptively Controlled Explicit Simulation (ACES) is a transient simulation methodology for integrated circuits and systems. An adaptively controlled explicit integration approximation is used which overcomes the stability problems encountered in earlier explicit techniques. Piecewise linear models are used for nonlinear devices, which allows efficient simulation of MOS, bipolar and BiMOS circuits. With the combination of generality, exploitation of circuit latency and ability to vary accuracy effectively, ACES provides an efficient environment for transient simulation of integrated circuits and systems.>

An approach to computing the time response of an arbitrary 3-D interconnect structure based on asymptotic waveform evaluation (AWE) is introduced. It has been implemented in a software tool called 3DAWE. To facilitate the application of AWE to a 3D RC mesh network model, the AWE formulation is rederived based on a nodal analysis approach. The ICCG matrix solver has been successfully applied in 3DAWE. It is shown that the typical transient response of a reasonably large 3D RC network can be obtained within a few minutes on a 15-MIPS computer using this program.>

An intuitive relationship between numerical integration algorithms and AWE is established. A small number of data points generated during a brief fixed timestep numerical integration of linear(ized) circuits are used to form sampled waveform integration, correction and extrapolation (SWICE) models. This method preserves the efficiency of the AWE technique, while increasing the accuracy and generality. The strengths of such an approach are illustrated from a theoretical view, as well as with practical examples.>

A problem inherent in methods for simulating distributed elements with the asymptotic waveform evaluation (AWE) technique is that they use complex exponentials to approximate pure delays in the time responses of transmission lines. The aproximation can lead to spurious ringing in the simulation results. This problem can be overcome within the context of a SPICE-based simulator. The generalized method of characteristics is used to derive an equivalent circuit model for a system of coupled lines. This allows the pure delay to be factored out; AWE can then be used to approximate the characteristic admittance, as well as the propagation functions of the lines. The AWE approximation can be simulated efficiently within a modified version of SPICE. Examples are presented to demonstrate that this technique is both accurate and faster than other methods.>

A general approach for modeling 3-D layout geometries is presented. In particular, the partial-element equivalent circuit (PEEC) technique has been used successfully to model interconnect structures for chips and packages. The technique, which is circuit based, permits the electrical modeling of arbitrary 3-D geometries and allows 3-D transmission line properties to be analyzed. Recently, the technique has been extended to include retardation and dielectric layers. The authors have experimented with the use of the asymptotic waveform evaluation (AWE) approach to speed up the solution of the resulting circuit equations.>

Asymptotic waveform evaluation (AWE) is a new method for approximating the behavior of linear(ized) circuits in either the time or the frequency domain in terms of a dominant pole/zero approximation. An efficient method for calculating the sensitivities of the poles and zeros found by AWE has been developed. Using the adjoint sensitivity method, it is possible to inexpensively compute the sensitivities of the poles and zeros with respect to all circuit parameters, as well as to suppressed circuit parasitics. The sensitivities of the approximate poles and zeros found by AWE show excellent correlation with those of the real circuit and provide useful information in both the time and the frequency domain.>

Switching transient estimation of interconnect is becoming over more important with increasing signal speeds and smaller device sizes. Asymptotic Waveform Evaluation (AWE) is a technique which can efficiently and accurately evaluate the response of linear interconnect. A novel modeling technique has been developed to incorporate the effects of nonlinear drivers on that transient response. This technique, based on matching the current waveform of the driving gate, is load independent. The method yields efficient and accurate results. 1 Motivation

Article ADAPTS: A digital transient simulation strategy for integrated circuits Share on Authors: Alexander D. Stein Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PennsylvaniaView Profile , Tuyen V. Nguyen Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PennsylvaniaView Profile , Binay J. George Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PennsylvaniaView Profile , Ronald A. Rohrer Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PennsylvaniaView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 26–31https://doi.org/10.1145/127601.127618Online:01 June 1991Publication History 17citation141DownloadsMetricsTotal Citations17Total Downloads141Last 12 Months2Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

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Both direct and adjoint methods are applied to the computation of time-domain transient sensitivities in the already efficient SPECS piecewise approximate circuit simulation environment. By exploiting the event-driven nature of SPECS, the computation, storage, and interpolation of the Jacobians that specify the appropriate linearized circuit during the forward simulation is not required to obtain sensitivities. Both direct and adjoint methods require only a marginal computational overhead and provide equivalent results. The choice of the method to use depends on the ratio of the number of outputs to the number of parameters. More parameters favor the adjoint method and more outputs favor the direct. The overall efficiency of both SPECS and its time-domain sensitivity extension allows it to be applied to realistic circuits that, due to their large size, had previously made such analysis impractical. Simulation results on industrial circuits of up to 1500 MOS transistors show that transient sensitivities can be efficiently computed for large circuits.>

A simulation methodology for the nonlinear transient analysis of electrical circuits is described. Equations are formulated on the tree/link basis. All branch and node variables are modeling to be piecewise approximate in time. Electronic devices are represented by empirical table models of I-V characteristics. The table models may be built at various levels of precision, and concomitant accuracy levels are reflected in the simulation results. Simulation accuracy may be varied on a branch-by-branch basis or global basis, this permitting the user to distribute computer resources in a meaningful manner. The simulation algorithm is event driven and fully exploits temporal sparsity in the underlying circuit equations. Mechanisms for dealing with steady-state situations and stiff circuits have been investigated. A prototype simulator, SPECS, has been developed and tested on large industrial integrated circuits. It has proven to be a reliable and efficient tool in the analysis of digital and mixed circuits.>

Asymptotic waveform evaluation (AWE) is a novel method to analyze linear(ized) circuits. It uses a form of Pade approximation rather than numerical integration to approximate the behavior of linear(ized) circuits in either the time or the frequency domain. Improvements are presented to the theory of AWE to avoid some inherent limitations of Pade approximation. A discussion is presented of the practical aspects that have arisen in the attempt to use AWE in a simulation program called AWEsim. Results are also presented of AWEsim that clearly demonstrate the advantage of AWE over traditional approaches to circuit simulation.>

Asymptotic waveform evaluation (AWE) is a novel method to approximate the behavior of linear(ized) circuits in either the time or the frequency domain in terms of a dominant pole/zero approximation. An efficient method for calculating the sensitivities of the poles and zeros found by AWE has been developed. Using the adjoint sensitivity method, it is possible to inexpensively compute the sensitivities of the poles and zeros with respect to all circuit parameters, as well as to circuit parasitics. The sensitivities of the poles and zeros show excellent correlation with the perturbation response, and can provide valuable feedback to the circuit designer.>

The incorporation of inductors in a piecewise approximate circuit simulator, enhancing the generality of such a tool, is presented. Most approximate timing simulators preclude inductors from the underlying circuit. Conventional simulators allow inductive effects, but are too inefficient to simulate very large circuits. The formulation presented allows the event-driven simulation of circuits containing inductors, capacitors and general nonlinear elements. The event processing algorithm is based on the conservation of flux and energy. The implementation was tested in a prototype addition to the SPECS simulation environment. In addition, the theory behind the incorporation of mutual inductors is presented. A few benchmarks were run to confirm the veracity of the model. Research into the automatic, dynamic determination of the optimum current resolution would cause the tool to be more efficient, as well as relieve the designer of choosing a current resolution for the inductors in the circuit.>

Asymptotic waveform evaluation (AWE) provides a generalized approach to linear RLC circuit response approximations. The RLC interconnect model may contain floating capacitors, grounded resistors, inductors, and even linear controlled sources. The transient portion of the response is approximated by matching the initial boundary conditions and the first 2q-1 moments of the exact response to a lower-order q-pole model. For the case of an RC tree model, a first-order AWE approximation reduces to the RC tree methods.>

Most timing analyzers rely upon a linear approximate interconnect model, typically an RC tree, to estimate efficiently the propagation delays for digital MOS integrated circuits. RC tree methods are adequate to analyze a large class of MOS circuits, but are not sufficient in general for high speed, dynamic and precharge MOS circuits. In addition bipolar logic and board level digital systems can have interconnect models which may not be compatible with RC tree topologies. In this paper we describe AWEsim, a variable refinement waveform estimator for generalized linear RLC approximate interconnect models.

Deterministic optimization programs are coming to be considered as viable alternatives for the placement of very large sea-of-gate, gate array and standard cell designs. A nets-as-points placement program has been described which provides competitive results in comparison with non-deterministic placement, and at a fraction of the run time. A new pseudo Steiner tree model for the gate placement about the netpoints, along with a virtual channel snap-to-grid procedure, provides results superior to the original nets-as-points placement program without requiring iterative improvement.

Transient sensitivity computation in SPECS (simulation program for electronic circuits and systems), which provides a unique capability both to enhance efficiency and to validate simulation results, is described. By using transient sensitivities with respect to the entries of piecewise constant (table) element models and suppressed parasitics, an initially crude and correspondingly quick simulation can be undertaken and then augmented if necessary for improved accuracy. More specifically, table models are refined and parasitics reintroduced only where required in the final analysis as indicated by sensitivity results. This overall approach increases confidence in the results of the SPECS simulation strategy which relies heavily on simplified models for its enhanced efficiency.>

Conventional circuit simulation methods are inflexible and slow, especially for large circuits. Piecewise approximate circuit simulation, an alternative that can be more efficient and allows variable accuracy in the simulation process, is discussed. Thus, the tradeoff between accuracy and CPU time is in the hands of the user. SPECS (simulation program for electronic circuits and systems) is the prototype implementation of a piecewise approximate, tree/link based, event driven, variable accuracy circuit simulation algorithm that uses table models for device evaluation. The models can be built at various levels of accuracy, and concomitant levels of precision are reflected in the simulation results. SPECS has been benchmarked on some large, industrial circuits and has proven to be an efficient and reliable simulator. However, it suffers a penalty in run time while simulating stiff circuits, or circuits with a wide range of time constants. The authors present enhanced algorithms used in SPECS to ensure efficient steady-state computation for stiff circuits.>

A linearized state-variable formulation of the lumped circuit simulation problem shows the results of some simpler related dc analyses to be useful in the time step size stability control of explicit integration algorithms. These analyses result also in a stable explicit integration algorithm that is often applicable. Because the various results obtained are amenable to simple physical interpretation, their use is not limited to state variable formulations of the lumped circuit simulation problem.

Following an efficient circuit analysis with ideal operational amplifier (op amp) models, approximate results can be rendered realistic in terms of related sensitivity/tolerance computations. Sensitivities of circuit responses to manufacturer specified op amp tolerances complete the analysis by providing nominal and worst-case in-specification output variations.