We discuss the problem of accountability when multiple parties cooperate towards an end result, such as multiple companies in a supply chain or departments of a government service under different authorities. In cases where a fully trusted central point does not exist, it is difficult to obtain a trusted audit trail of a workflow when each individual participant is unaccountable to all others. We propose AudiWFlow, an auditing architecture that makes participants accountable for their contributions in a distributed workflow. Our scheme provides confidentiality in most cases, collusion detection, and availability of evidence after the workflow terminates. AudiWFlow is based on verifiable secret sharing and real-time peer-to-peer verification of records; it further supports multiple levels of assurance to meet a desired trade-off between the availability of evidence and the overhead resulting from the auditing approach. We propose and evaluate two implementation approaches for AudiWFlow. The first one is fully distributed except for a central auxiliary point that, nevertheless, needs only a low level of trust. The second one is based on smart contracts running on a public blockchain, which is able to remove the need for any central point but requires integration with a blockchain.

This paper introduces an “Indicator of Risk (IoR) Library” that leverages the MITRE ATT&CK for Industrial Control Systems (ICS) knowledge base to support continuous risk monitoring. This allows also making use of variables that are already being monitored to analyse risks in a continuous basis. IoRs broaden the concept of Indicators of Compromise by combining detection strategies with probabilistic inference as a tool for quantifying cyber-security risks. The latest version of the Library has 95 IoRs and has been reviewed by professionals from three major companies and cross-referenced against detection use-cases implemented by other researchers to validate its potential to identify variables for monitoring cyber-risks in ICS.

The continuous operation of an industrial process, such as water treatment or power generation, is governed by an Industrial Control System (ICS). Cyber-attacks on industrial networks are of growing concern because of the disruption they can cause, leading to loss of revenue, and the possibility of harm to workers, plant and surroundings. Operators therefore need a Network Intrusion Detection System (NIDS) to analyse industrial network traffic in real time for adversarial behaviour. Machine Learning (ML) is applicable to the problem of network intrusion detection. This paper investigates the possibility of training an ML-based NIDS for an ICS (specifically, the well-known Secure Water Treatment testbed) by combining network traffic data and physical process data. In the supplied dataset, data had already been labelled “according to normal and abnormal behaviours”; the labelling of data collected around the start and end of each attack was scrutinized and, where found to be problematic, labelled data were excluded in order to improve the effectiveness of supervised learning. The ML technique of “Learning using Privileged Information” was evaluated and found to be superior to six baseline ML algorithms trained on network traffic data alone.

We tackle the problem of sharing eHealth data across different jurisdictions. As a general rule, and due to the sensitive nature of the information, different national regulations impose severe limits on what can be exchanged, even in case of emergencies. Furthermore, different systems in different jurisdictions do not communicate. We propose BRUE as a scheme that allows eHealth data to be securely exchanged, with the data subject always in the position of mediation. We combine several technologies, namely, Blockchain, OAuth and User-Managed Access, and concept Receipts, to achieve our aim.

Lack of skilled digital forensic professionals is seriously affecting the everyday life of everyone as businesses and law enforcement are struggling to fill the bare minimum number of digital investigator positions. This skills shortage can hinder incident response, with organizations failing to put effective measures in place following a cyber-attack or to gather the digital evidence that could lead to the successful prosecution of malicious insiders and cyber-criminals. It therefore makes the connected world less secure and digital economies less reliable, affecting everyone in their ecosystems. The commercial and public sectors are looking to higher education institutions to produce quality graduates equipped to enter the digital forensics profession. This paper presents our proposed research-led, practice-driven digital forensics curriculum. The curriculum is designed to respond to employers’ needs and is built on the experience of running a successful Cyber Security program at Birmingham City University in the industrial heartland of the UK. All students will take a common set of modules in the first semester, but will be given the opportunity to specialize in digital forensics in the second semester and in their summer project, enabling them to graduate with the degree of MSc Digital Forensics.

Synthesis of asynchronous logic using the tool Petrify requires a state graph with a complete state coding. It is common for specifications to exhibit concurrent outputs, but Petrify is sometimes unable to resolve the state coding conflicts that arise as a result, and hence cannot synthesise a circuit. A pair of decomposition heuristics (expressed in the language of Delay-Insensitive Sequential Processes) are given that helps one to obtain a synthesisable specification. The second heuristic has been successfully applied to a set of nine benchmarks to obtain significant reductions both in area and in synthesis time, compared with synthesis performed on the original specifications.

Delay insensitive interfacing was first demonstrated on the macromodules project in the 1960's, but globally synchronous (clocked) schemes have so far dominated the VLSI era. In deep sub-micron technologies, problems of clock skew, including excessive size and power consumption of black buffers, and heterogeneity of systems on a chip are rekindling an interest in global asynchrony. DI-Algebra is presented here as a language for the specification of modules with delay-insensitive interfaces. Such modules can be implemented either in synchronous or in asynchronous logic. A design flow is also illustrated in which specifications are automatically translated into Petri nets, validated and synthesised into asynchronous logic.

A comparison with synchronous circuits suggests four opportunities for the application of asynchronous circuits: high performance, low power; improved noise and electromagnetic compatibility (EMC) properties, and a natural match with heterogeneous system timing. In this overview paper each opportunity is reviewed in some detail, illustrated by examples, compared with synchronous alternatives, and accompanied by numerous pointers to the literature. Conditions for applying asynchronous circuit technology, such as the existence and availability of computer-aided design (CAD) tools, circuit libraries, and effective test approaches, are discussed briefly. Asynchronous circuits do offer advantages for many applications, and their design methods and tools are now starting to become mature.

This technology review explores the behavioral and structural design domains for asynchronous circuits and systems. It proceeds bottom up, introducing relevant concepts, terminology and techniques through a succession of simple examples. There are seven main points: 1) Signal transitions provide a key to understanding the switching behavior of asynchronous logic. 2) Burst-mode circuits and speed-independent control circuits offer reliable operation that is free from glitches. 3) Various notations are available for specification of control circuitry and as a starting point for logic synthesis. 4) Bundled data and delay-insensitive coding schemes are suitable for representing data because they address the issues of data validity and completion detection. 5) Asynchronous networks, constructed from modules and channels, provide a systems architecture for asynchronous design. 6) Handshaking on channels, which controls data communication and synchronization between modules, is implemented using signal transitions. 7) The translation of algorithmic descriptions into asynchronous networks facilitates an automated approach to large-scale system design.

No abstract.

Abstract One approach to the design of VLSI systems involves the use of asynchronous circuits that communicate by handshaking with each other. The control circuitry generated when following this approach often includes large trees of binary sequencer components. This paper demonstrates that there is scope here for optimization (in order to improve size, speed and energy consumption). Indeed, an industrial-strength silicon compiler has now been modified to take advantage of this fact. The problem that is addressed concerns the design of efficient control circuits that sequenceNfour-phase handshakes (N> 2). Muller's speed-independent discipline facilitates the design of such circuits. SI-Algebra, a calculus that supports that discipline, is used to specify the problem and to verify (using recursion-induction) various implementations. Simple counting arguments at the gate level establish that optimization using these implementations is worthwhile.

An asynchronous arbiter dynamically allocates a resource in response to requests from processes. Glitch-free operation when two requests arrive concurrently is possible in MOS technologies. Multiway arbitration using a request-grant-release-acknowledge protocol can be achieved by connecting together two-way arbiters (mutual exclusion and tree arbiter elements). We have devised a fast and compact design for the tree arbiter element which offers eager forward-propagation of requests. It compares favorably with a well-known design in which request propagation must wait for arbitration to complete. Our analysis and simulations also suggest that no performance improvement will be obtained by incorporating eager acknowledgment of releases. All of the designs considered in this paper are speed-independent, a formal property of a network of elements which can be taken as a positive indication of their robustness.

Abstract The CICS/ESA Intercommunication Guide is a source of information about distributed CICS systems. Among other things, it describes how an application program running on one system can issue a command that will be shipped to a remote system. A resource manager located at the remote system will execute the command and ship back a response. This paper presents a formal specification of the above interaction between application programs and resource managers. Some familiarity with the Z specification language is assumed. The structure of the specification illustrates how it is possible to address separately, and later combine, different aspects of a complex system, including its distributed nature.