The issue of handling multiple embedded 1149.1-compliant TAP controllers (as part of embedded cores) in a 1149.1-compliant IC, has received significant attention, in recent times. The Hierarchical TAP (HTAP) architecture, previously developed by this author, provides a systematic solution to this problem, by allowing multiple embedded TAPs to share one set of 1149.1-specified test pins on the IC. The HTAP architecture requires an augmented version of the 1149.1-specified TAP-designated the Snoopy TAP (SNTAP)-in the top-level of the design hierarchy, that handles 1149.1-specified TAP functions for the non-TAP'ed parts of the IC, and performs arbitration of the shared IC pins between multiple embedded TAPs. Previously, a mechanism was developed to wake up the SNTAP using a simple string of constant values (0 or 1) on the TMS input. Two new mechanisms to wake up SNTAP by means of an instruction scanned in, are described in this report. Both mechanisms allow embedded 1149.1-compliant TAP's to be used in a hierarchical design, as is, without any hardware modification. Moreover, both mechanisms enable reuse of the test program from the embedded TAP'ed cores, without any modification. The instructions to wake up the SNTAP-to switch access to different TAP-ed cores-can be simply inserted in-between the test programs for the embedded cores.

The rapid emergence of reusable core-based designs, in the last few years, poses new challenges to the IEEE test access standard 1149.1. Due to widespread industrial acceptance of 1149.1 standard, ICs are now expected to be 1149.1-compliant. At the same time, a typical IC, like the TMS470 microcontroller manufactured by TI, often contains multiple cores with built-in 1149.1 compliant Test Access Port (TAP), as well as significant amounts of non-core logic, which does not have any built-in test access mechanism. In this paper, we present a new TAP design that enables systematic integration of TAP'ed cores with non-TAP'ed logic, and makes the total IC 1149.1 compliant, at the same time. This TAP design, designated Hierarchical Test Access Port (HTAP), has exactly the same I/O pin specifications as an 1149.1-compliant TAP, and can either serve as an 1149.1-compliant TAP, or act as an arbitrator between existing TAPs in the Embedded cores. Behavior of the HTAP-whether to act as a TAP or as an arbitrator of TAPs-is controlled via the TMS input pin.

The inherent computational redundancy in discrete-time LTI-FIR system response computations in Digital Signal Processing have been exploited in a variety of ways to minimize the computational complexity. We present an improved algorithm-level computational optimization that uses sorted recursive differences between coefficients representing the system transfer function with a Floating-Point number representation to extract maximum benefits from this redundancy. A can be applied to any LTI-FIR system and there is no deterioration in accuracy compared 20 directly using the coefficients. The results for several practical FIR systems show that there is a significant reduction in the computational complexity, hence power consumed, using this technique.

A new test generation technique for path delay faults in circuits employing scan/hold type flip-flops is presented. Reduced ordered binary decision diagrams (ROBDDs) are used to represent Boolean functions realized by all signals in the circuit, as well as to represent the constraints to be satisfied by the delay fault test. Two faults are considered for each path in the circuit. For each fault, a pair of constraint functions, corresponding to the two time frames that constitute a transition, is evaluated. If the constraint function in the second time frame is non-null, robust-hazard-free-test generation for the delay fault is attempted. A robust test thus generated belongs either to the class of fully transitional path (FTP) tests or to the class of single input transition (SIT) tests. If a robust test cannot be found, the existence of a non-robust test is checked. Boolean algebraic manipulation of the constraint functions guarantees that if neither robust nor non-robust tests exist, the fault is undetectable. In its present form the method is applicable to all circuits that are amenable to analysis using ROBDDs. An implementation of this technique is used to analyze delay fault testability of ISCAS '89 benchmark circuits. These results show that the algebraic technique is one to two orders of magnitude faster than previously reported methods based on branch-and-bound algorithms.>

We present a new algorithm for generating tests for single stuck line (SSL) faults in combinational logic circuits using a combination of Boolean and path-oriented techniques. We use Boolean techniques employing the ordered binary decision diagram (BDD) to limit the effect of hard faults on the performance of the algorithm. We use path-oriented techniques similar to those in conventional test generation algorithms to limit the number of algebraic operations that must be performed. The test set generated for each fault is exhaustive in the sense that we find all test patterns which make the fault observable at some primary output. We implemented the algorithm as the program TSUNAMI and applied it to the standard ISCAS '85 and ISCAS '89 benchmark circuits. Results indicate that for circuits which are amenable to analysis by BDD's, TSUNAMI performs significantly better than conventional algorithms such as FAN or EST in generating tests for all targeted faults. Moreover, TSUNAMI finds a large set of test vectors for each fault. The program can easily manipulate these sets of vectors to produce test vectors which test many faults. As a result, we are able to compress the sets of vectors into a very small total number of patterns.

This paper describes an ROBDD-based distributed test generation algorithm for combinational circuits. This technique lends itself to a natural partitioning of both the fault list and the circuit across processors. A preliminary implementation on an Ethernet-connected SPARC2 workstation cluster shows the feasibility of the method.

A new technique to parallelize fault simulation for combinational digital circuits, suitable for message passing based parallel processors, is described. Speedup is achieved via combined use of data flow analysis and pipeline-like communication between processors. Unlike previous algorithms based on fault partitioning only, this approach uses both circuit and fault partitioning, and is both memory- and time-efficient with increasing number of processors.>

The authors present a high-speed fault simulator, called CMP3F, that performs parallel-pattern, parallel-fault simulation, implemented on the Connection Machine (CM). Unlike conventional parallel pattern or parallel fault simulators, CMP3F can dynamically choose the fault set size as well as the number of vectors being simulated in parallel. Hence, the fault simulation process is split into several phases. The first phase primarily uses fault-list partitioning because, initially, the fault-list size dominates the fault simulation time. If fault dropping is allowed, CMP3F goes through a number of subsequent phases as the fault list becomes smaller, simulating an increasing number of distinct sets of vectors in parallel. Thus, CMP3F avoids useless computations when a small number of faults are present and maintains nearly linear speedup with an increasing number of processors. Experimental data obtained using ISCAS85 benchmark circuits suggest that CMP3F implemented on a fully configured 64 K-node CM, will perform fault simulation one to two orders of magnitude faster than most existing fault simulators.>

Recent work has shown that test generation complexity and test set size can be reduced by high-level analysis that exploits the natural design hierarchy found in digital circuits. A design modification approach aimed at facilitating high-level testing by enhancing circuit regularity is proposed. This approach can improve the testability of a broad class of useful array- and tree-like circuits, including counters, decoders, and arithmetic logic units (ALUs). This is demonstrated for the specific case of decoders and decoding trees, where the test set size is reduced from O(2/sup n/) to O(n). A systematic design technique called level separation (LS) is presented for generalized tree circuits, which are useful for fast implementation of arithmetic functions like addition and multiplication. Design for testability (DFT) and hierarchical test generation are shown to reduce the test size from O(n) to O(log/sub 2/ n) for such circuits. A case study of a 16-b four-function ALU is presented to illustrate the utility of the LS method.>