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Haruo Niimi

dblp:56/5602 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2002
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-authorHuman-computer interaction and ubiquitous computing · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer graphics and multimedia
1 paper
Rendering · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Rendering
hidden surface removal
0.011984
A parallel processor system for three-dimensional color graphics · SIGGRAPH 1984
Rendering › hidden surface removal
scan-line algorithms
0.011984
A parallel processor system for three-dimensional color graphics · SIGGRAPH 1984

Methods — techniques the papers use, named apart from their topics

raster-scan display · 0.0hierarchical multiprocessor · 0.0
YearPublicationVenuePosition
2002 Development of an Education Tool for Computer System
abstract
An education tool has been developed to explain internal behavior and structure of computer graphically. It is written in Java Language and designed for students to understand how computer works in the classroom lecture of information science. This paper describes some characteristics of our education tool and improvement of its facilities, especially embedded mail handling module for information exchange between teacher and students.
Yoshiro Imai, Shinji Tomita, Haruo Niimi, Hitoshi Inomo, Wataru Shiraki
ICCE3
1984 A parallel processor system for three-dimensional color graphics
abstract
This paper describes the hardware architecture and the employed algorithm of a parallel processor system for three-dimensional color graphics. The design goal of the system is to generate realistic images of three-dimensional environments on a raster-scan video display in real-time. In order to achieve this goal, the system is constructed as a two-level hierarchical multi-processor system which is particularly suited to incorporate scan-line algorithm for hidden surface elimination. The system consists of several Scan-Line Processors (SLPs), each of which controls several slave PiXel Processors (PXPs). The SLP prepares the specific data structure relevant to each scan line, while the PXP manipulates every pixel data in its own territory. Internal hardware structures of the SLP and the PXP are quite different, being designed for their dedicated tasks.
Haruo Niimi, Yoshiro Imai, Masayoshi Murakami, Shinji Tomita, Hiroshi Hagiwara
SIGGRAPH1