The combination of digital pathology and artificial intelligence attracts more and more attention. In order to take into account the global and detailed textural information, recent works proposed to use whole-slide images (WSI) with more than 10 million pixels to train artificial neural networks in pursuit of a high-precision model. However, such an approach faces new technical challenges. When researchers conduct neural network training on a graphics processing unit (GPU), the extremely high spatial resolution of WSI and the large amount of intermediate data generated during the training process exceed the memory capacity of the GPU. Therefore, streaming convolutional neural network (SCNN) was proposed to disassemble a large image into multiple smaller patches that can be forward and backward propagated under the limitation of GPU memory during the training process. However, in a multi-GPU high-performance computing (HPC) system, when the central processing unit (CPU) performs data preprocessing for the distributed training of multiple GPUs, decoding large images and data augmentation consume a lot of memory and CPU time, resulting in a performance bottleneck.This paper first presents a multithreaded image decoder optimized for multi-core CPUs to speedup WSI loading. We also propose a patch-level data augmentation algorithm and implement it on a dedicated GPU to distribute the augmented data to other GPUs for training the SCNN. We use the above method to train the ResNet-50 SCNN model by learning from the TCGA-LUAD and TCGA-LUSC datasets published by The Cancer Genome Atlas. In comparison to training the SCNN on multiple GPUs using the regular distributed data parallelism, our method can save up to 92.8% of memory and increase the training speed by up to 242.5% when training with 8 A100 GPUs on the NVIDIA DGX-A100 system.

A three-dimensional (3D) integrated circuit (IC) with multiple dies vertically connected by through-silicon-via (TSV) offers many benefits over current 2D ICs. Multicore logic-memory die stacking has been considered as one candidate for 3D ICs by utilizing the TSV to provide high data bandwidth between logic and memory. However, 3D ICs suffer from the low-yield issue. This article proposes effective yield-enhancement techniques for multicore die-stacked 3D ICs. Two reconfiguration schemes are proposed to logically swap the positions of cores in the dies of 3D ICs such that the yield of 3D ICs is increased. Two algorithms also are proposed to determine the reconfiguration effectively. Simulation results show that the proposed reconfiguration schemes can achieve a yield gain ranging from 1% to 11%.

3-D integration using through silicon via is an emerging technology for integrated circuit designs. Random access memory (RAM) is one good candidate for the application of 3-D integration technology. However, yield will be a key challenge for the volume production of 3-D RAMs. In this paper, we present yield-enhancement techniques for 3-D RAMs. An interdie redundancy scheme is proposed to improve the yield of 3-D RAMs. Three stacking flows with respect to different bonding technologies for 3-D RAMs with interdie redundancy are proposed as well. Finally, a built-in self-repair (BISR) scheme is proposed to perform the repair of 3-D RAMs with interdie redundancies. The BISR circuits in two stacked dies can work together to allocate interdie redundancies. Simulation results show that the proposed yield-enhancement techniques can effectively improve the yield of 3-D RAMs.

Three-dimensional (3D) integration using through-silicon via (TSV) is an emerging technique for integrated circuit (IC) designs. A 3D IC consists of multiple dies vertically connected by TSVs. To ensure the yield of 3D ICs, each die should be tested before it is stacked, i.e., the pre-bond test. Typically, test pads are implemented in the die under test for the pre-bond test due to the limitation of current probing technologies. However, the additional test pads incur additional die area. In this paper, therefore, we propose a test cost optimization technique for the pre-bond test of 3D ICs. This technique attempts to minimize the number required power pads of each die in a wafer and the overall test time of the wafer. Simulation results show that reducing power pads can effectively reduce the number of required test pads and the wafer test time.

3-D integration using through-silicon-via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. Test and yield are two big issues for volume production of 3-D ICs. In this paper, we propose a built-in self-repair (BISR) scheme to test and repair TSVs in 3-D ICs. The BISR scheme, arranging the TSVs into arrays similar to memories, can effectively enhance the yield of TSVs in a 3-D IC such that the yield of the 3-D IC is boosted. Furthermore, a global fusing methodology is proposed to reduce the requirement of fuses. Simulation and analysis results show that the proposed BISR scheme can drastically reduce the area cost and test time in comparison with an existing TSV repair scheme for the same final yield of TSVs under repair. For a 3-D wide-IO DRAM with 512 TSVs, for example, the proposed repair scheme can achieve 32.4% area reduction and 73.4% test time reduction.

This paper proposes an enhanced IEEE 1500 test wrapper to support the testing and diagnosis of the single-port or multi-port RAM core attached to the enhanced IEEE 1500 test wrapper without incurring large area overhead to small memories. Effective test time reduction techniques for the proposed test scheme are also proposed. Simulation results show that the additional area cost for implementing the enhanced IEEE 1500 test wrapper is only about 0.58% for a 64 K-bit single-port RAM and only 0.57% for a 64 K-bit two-port RAM in 90-nm technology.

This paper proposes a Pai-Sigma matchline scheme to reduce the compare (search) power of a ternary content addressable memory (TCAM). The proposed matchline does not incur the issues of charge sharing and short circuit current, which typically exist in the hybrid nand-nor matchline. Moreover, the switching activity of the search lines of a TCAM with the proposed matchlines is low. A 32×64-bit TCAM with the Pai-Sigma matchlines is implemented to demonstrate the low-power feature. Results show that the compare power of the TCAM can achieve 60% energy reduction compared with the conventional nor-type TCAM. Also, the energy consumption per bit per search of the TCAM is only 2.287 fJ/bit/search.

Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs offers many benefits over current 2D ICs. However, the testing of 3D ICs is much more difficult than that of 2D ICs. In this paper, we propose a cost-effective built-in self-test circuit (BIST) to test TSVs of a 3D IC. The BIST scheme, arranging the TSVs into arrays similar to memory, has the features of low test/diagnosis time and low silicon area cost. Simulation results show that the area overhead of the BIST circuit implemented with 0.18μm CMOS technology for a 16×32 TSV array in which each TSV cell size is 45μm2is 2.24%. Also, the BIST needs only 130 clock cycles to test the TSV array with stuck-at faults. In comparison with the IEEE 1500-based test approach, the BIST scheme can achieve 85.2% area cost and 93.6% test time reduction.

Modern processor and computation-intensive chips typically use the design style of multi-core chip architecture with identical logic and memory cores. Although memory built-in self-test (BIST) is a mature technique for testing embedded memories, testing multiple small memories using small area cost is still a challenge. This paper proposes a low area-cost BIST scheme for an array of memories and interconnections between memory cores and logic cores. To reduce the area cost without incurring long testing time, the BIST scheme tests multiple identical memories in a pipeline and each memory with a serial test interface. Experimental results show that the proposed BIST scheme has small area cost. For example, the proposed BIST scheme for 16 1024×64-bit RAMs only needs about 0.89% hardware overhead.

This paper presents a march-like testTAC-Pto cover comparison faults of ternary content addressable memories (TCAMs) with asymmetric cells. The TAC-Ponly requires 4NWrite operations and (3N+2B) Compare operations for anN×B-bit TCAM with Hit and priority address encoder outputs. We show that the test also can cover search time failures induced by process variation in the comparison circuit of a TCAM. Furthermore, a test TMFfor match failures induced by the process variation in the comparison circuit of a TCAM is also presented.

Built-in self-repair (BISR) techniques are widely used to enhance the yield of embedded random access memories (RAMs). Fault-location ability of test algorithms executed by a BISR circuit has heavy impact on the repair efficiency of the BISR circuit. This paper proposes a defect-aware BISR (DABISR) scheme for single-port RAMs (SPRAMs) and multi-port RAMs (MPRAMs) in system chips. Multiple RAMs can share a DABISR such that the area cost of DABISR is drastically reduced. We also present two defect-location algorithms (DLAs) for identification of bridge defects between word-lines and bit-lines of MPRAMs. The DABISR can perform DLAs to locate bridge defects such that it can provide high repair efficiency. For example, simulation results show that if a faulty two-port RAM has 20% inter-port faults, the DLAs can help to gain 8.4-14.4% increase of repair rate for different redundancy configurations. In comparison with an existing shared BISR scheme, however, the DABISR only incurs about 0.34% additional area overhead to support the function of DLAs.

Three-dimensional (3-D) integration is an emerging integrated circuit technology. It offers many advantages over the 2-D integration. However, testing 3-D chips is a very challenging job. The testing of a 3-D chip includes the testing for known good die (KGD) and the testing of stacked 3-D chip. This paper analyzes the test complexities of 3-D random access memories (RAMs) and content addressable memories (CAMs) in the phase of testing of stacked 3-D ICs with functional faults. Analysis results show that the 3-D CAMs and RAMs can be tested with lower test complexity than the 2-D ones. Furthermore, simple design-for-testability (DFT) methods are proposed to reduce the test complexity of 3-D RAMs and CAMs further.

Ternary content addressable memory (TCAM) is a key component in various applications for its fast lookup operation. Symmetric and asymmetric TCAM cells are two widely used cells for implementing a TCAM array. This paper presents several comparison fault models of TCAMs with asymmetric cells based on electrical defects. Some new comparison faults which do not exist in a TCAM with symmetric cells are found. A march-like test algorithm is also proposed to cover the defined comparison faults. The test algorithm consists of 8N Write operations and (3N + 2B) Compare operations for an N×B-bit TCAM with Hit output only.

Multicore system-on-chip (SOC) design is widely used for current high-performance applications. Multicore SOCs typically include a large amount of homogeneous memory cores (i.e., memory cores have the same size and configuration). This paper proposes a pipelined built-in self-test (PBIST) scheme for homogeneous memory cores in multicore SOCs. A PBIST circuit can be shared by clustered multiple homogeneous memories. This drastically reduces the hardware overhead of the PBIST circuit. A systematic procedure for converting a march test into a pipelined march test is also proposed. Experimental results show that the area overhead of a pipelined BIST for eight homogeneous 1k times 128-bit memories is only about 0.71%.

Built-in self-repair (BISR) techniques have been widely used for enhancing the yield of embedded memories. This paper presents an efficient BISR scheme for multiport RAMs (MPRAMs). The BISR scheme has a defect-location module (DLM) executing a defect-location algorithm to locate inter-port defects. This enhances the fault-location capability of the applied test algorithm with only a few amount of cost of testing time. A built-in redundancy analyzer (BIRA) executing a proposed redundancy analysis algorithm is also proposed to allocate two-dimension redundancy of MPRAMs. Experimental results show that if a faulty MPRAM has 20% inter-port faults, the DLM can boost the increment of repair rate from 8.4% to 14.4% for different redundancy configurations. The area cost of the BIRA and DLM is small, it is only about 1% for a 4096 times 128-bit MPRAM with 1 spare row and 1 spare IO.

With the shrinking feature size and the growing density, testing neighborhood pattern-sensitive faults (NPSFs) of integrated circuits is more and more important, especially testing NPSFs of semiconductor memories. This paper presents a test algorithm for detecting the active NPSFs (ANPSFs) in ternary content addressable memories (TCAMs). Due to the special TCAM cell structure, unique test algorithm with only march-based test operations or only two-group test operations is not efficient. We propose a test methodology with both march-based and two-group tests to cover 100% ANPSFs in TCAMs. The total test complexity is 156 for an -bit TCAM. Also, no TCAM circuit modification is needed to support the proposed test methodology.