A next-generation deep-space network is currently under consideration by the National Aeronautics and Space Administration. Building upon its many past successes, this network will be required to meet the needs of current and planned missions. These will, no doubt, include the familiar suite of telemetry, command, tracking, and navigation services, with performance levels derived from analysis of the probable future mission set. Additionally, it will be expected to provide enabling capabilities for missions still on the drawing boards. Traditionally, the network serves the robotic deep-space exploration fleet. However, at this time, consideration of the special needs of planned future human lunar missions is appropriate, as well as the evolution to the eventual human exploration of Mars.

Three different finite-field multipliers are presented: (1) a dual-basis multiplier due to E.R. Berlekamp (1982); the Massey-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard basis multiplier. These algorithms are chosen because each has its own distinct features that apply most suitably in particular areas. They are implemented on silicon chips with NMOS technology so that the multiplier most desirable for VLSI implementation can readily be ascertained.>

A new VLSI design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous design is replaced by a simple time domain algorithm. A new architecture which realizes such algorithm permits efficient pipeline processing with a minimum of circuits. A systolic array is also developed to perform erasure corrections in the new design. A modified form of Euclid's algorithm is developed with a new architecture which maintains a real-time throughput rate with less transistors. Such improvements results in both an enhanced capability and significant reduction in silicon area, thereby making it possible to build a pipeline (255,223) RS decoder on a single VLSI chip.

A pipeline structure of a transform decoder similar to a systolic array is developed to decode Reed-Solomon (RS) codes. The error locator polynomial is computed by a modified Euclid's algorithm which avoids computing inverse field elements. The new decoder is regular and simple, and naturally suitable for VLSI implementation.

A pipeline structure of a transform decoder similar to a systolic array is developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error-locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new coder is regular and simple, and naturally suitable for VLSI implementation. An example illustrating both the pipeline and systolic array aspects of this decoder structure is given for a RS code.

Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that can be easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. In this paper, a pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal basis representation used together with this multiplier, a pipeline architecture is developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable, and therefore, naturally suitable for VLSI implementation.

Berlekamp has developed for the California Institute of Technology Jet Propulsion Laboratory (JPL) a bit-serial multiplication algorithm for the encoding of Reed-Solomon (RS) codes, using a dual basis over a Galois field. The conventional RS encoder for long codes often requires lookup tables to perform multiplication of two field elements. Berlekamp's algorithm requires only shifting and EXCLUSIVE OR operations. It is shown in this paper that the new dual-basis (255,223) RS encoder can be realized readily on a single VLSI chip with NMOS technology.

One way to increase the amount of data that can be received from weak signal sources (such as spacecraft in the vicinity of the outer planets) is to array several ground antennas in such a way as to increase the total effective aperture of the receiving system. One such method is virtual center arraying (VCA). In VCA, a combined carrier reference is derived at a point that is, conceptually, the geometric center of the array. This point need not coincide with any of the actual antennas of the array. This paper includes a noise analysis of the VCA system and exhibits formulas for the phase jitter as a function of loop bandwidths and the amount of loop damping. If the ratio of the loop bandwidths of the center loop to the vertex loops is greater than 100, then the jitter is very nearly equal to that expected for ideal combined carrier referencing.

An algorithm is presented which enables one ReedSolomon decoder to process other Reed-Solomon encoded data from a different code. All that is required is that both codes have the same length, the same rate, and the same field of coefficients.