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Megha Sangtani

dblp:56/5979 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2011
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 70% Electronic design automation · 30%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design
floorplanning
0.112011
Floorplanning for Partially Reconfigurable FPGAs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011
Reconfigurable computing and FPGAs
FPGA physical design
0.112011
Floorplanning for Partially Reconfigurable FPGAs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011
Reconfigurable computing and FPGAs › dynamic reconfiguration
partial reconfiguration
0.112011
Floorplanning for Partially Reconfigurable FPGAs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011
Reconfigurable computing and FPGAs › dynamic reconfiguration
reconfiguration overhead reduction
0.112011
Floorplanning for Partially Reconfigurable FPGAs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011
Electronic design automation
physical design
0.012011
Floorplanning for Partially Reconfigurable FPGAs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011

Methods — techniques the papers use, named apart from their topics

global floorplan generation · 0.1
YearPublicationVenuePosition
2011 Floorplanning for Partially Reconfigurable FPGAs
abstract
Partial reconfiguration on heterogeneous field-programmable gate arrays with millions of gates yields better utilization of its different types of resources by swapping in and out the appropriate modules of one or more applications at any instant of time. Given a schedule of sub-task instances where each instance is specified as a netlist of active modules, reconfiguration overhead can be reduced by fixing the position and shapes of modules common across all instances. We propose a global floorplan generation method PartialHeteroFP to obtain same positions for the common modules across all instances such that the heterogeneous resource requirements of all modules in each instance are satisfied, and the total half-perimeter wirelength over all instances is minimal. Experimental results establish that the proposed PartialHeteroFP produces floorplans very fast, with 100% match of common modules and thereby minimizing the partial reconfiguration overhead.
Pritha Banerjee 0001, Megha Sangtani, Susmita Sur-Kolay
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2