This paper proposes efficient trimmed-sample Monte Carlo (TSMC) methodology and novel yield-aware design flow for analog circuits. This approach focuses on "trimming simulation samples" to speedup MC analysis. The best possible yield and the worst performance are provided "before" MC simulations such that designers can stop MC analysis and start improving circuits earlier. Moreover, this work can combine with variance reduction techniques or low discrepancy sequences to reduce the MC simulation cost further. Using Latin Hypercube Sampling as an example, this approach gives 29x to 54x speedup over traditional MC analysis and the yield estimation errors are all smaller than 1%. For analog system designs, the proposed flow is still efficient for high-level MC analysis, as demonstrated by a PLL system.

In this paper, we present a novel configurable analog routing methodology for more efficient analog layout automation. By the help of OpenAccess constraint group format, the technology process rules and analog layout design intention/constraints are unified through schematic level to layout level. In contrast to self-defined constraint format in prior arts, proposed approach manipulates the analog routing characteristic based on the unified constraints. In different circuit hierarchies defined by circuit designers or extracted by existing placement, the hierarchical structure is formed as specific analog layout constraint groups. This work efficiently facilitates analog routing strategy which honors the specific analog constraints. By practicing on an analog functional block of tsmc 40nm SoC design which guarantees to be legalized and satisfies required analog constraints by DRC/LVS and post-layout simulation respectively, the results in wire matching for signal integrity show that the different routing priority generated by our approach can have significant performance impact.

A chip-level transient power analysis methodology for the 700 MHz PowerPC/sup TM/ microprocessor has been presented. Transistor-level simulation is used for best accuracy, while input vectors are gathered at the architectural level from certain applications. The IVP is used to describe the sequence of instructions that drive the applications under architecture-specific constraints. The generated cycle-based logic behaviors are then mapped to the timing-based input vectors to regenerate the timing relationship between signals. Algorithms have been presented for simulating the transient power. This methodology can simulate the blocks in a hierarchical manner, while the accuracy is preserved. By fetching the logic values from the AET file, the simulation can start at any user specified cycle to handle RTX state preload and to avoid simulation time waste at the initialization period. Three simulation cases have been studied, including a large custom array, an FPU, and the full chip including IR-drop analysis. This transient power analysis methodology has been successfully employed along the course of PowerPC/sup TM/ development for the power-aware design of the next-generation microprocessor.

In this paper, we present a temperature-aware simulation environment, iTAS, which has been developed for the design of thermally reliable ultra-large scale integrated (ULSI) chips. This environment provides advisory information from the early chip design phase to the post-layout analysis phase. Several important applications, including temperature-sensitive timing analysis, efficient on-chip hot-spot identification, and thermally reliable package design are addressed, iTAS can be used not only for reliability checking, but also for better thermal engineering to enhance the overall chip performance.

In this paper, we present a method to efficiently identify the on-chip hot spots in ULSI circuits. A set of mathematical formulae were derived in analytical forms so that local temperature information can be fetched quickly. These formulae were based on the Green's function and error function approximation, and the resulting equations were further simplified to a tractable level by asserting different constraints. Experimental result shows that this method is able to accurately locate the hot spots with little time complexity. It is particularly useful for temperature-driven circuit macro placement in the early chip design phase, for which a large number of design iterations are needed and simulation efficiency is required.

In this paper, we present a new chip-level electrothermal timing simulator for CMOS VLSI circuits. Given the chip layout, the packaging specification, and the periodic input signal pattern, it finds the on-chip steady-state temperature profile and the resulting circuit performance. A tester chip has been designed for verification of ILLIADS-T, and very good agreement between simulation and experiment was found. Using this electrothermal simulator, temperature-dependent reliability and timing problems of VLSI circuits can be accurately identified.

In this paper, we present a new electromigration reliability diagnosis tool (iTEM) for CMOS VLSI circuits. Unlike previous electromigration reliability tools, iTEM can estimate the interconnect temperature rise due to joule heating and heat conduction from the substrate using a newly developed lumped thermal model. By including the temperature effect, iTEM provides much more accurate electromigration reliability diagnosis. Moreover, it is computationally efficient, and can analyze circuit layouts containing tens of thousands of transistors on a desktop workstation.

In this paper, we present the first chip-level electrothermal simulator, iCET. For a given chip layout, packaging material, user-specified input signal patterns, and thermal boundary conditions, it automatically finds the CMOS on-chip steady-state temperature profile and the resulting circuit performance. iCET has been tested on several circuits and it can efficiently analyze layouts containing tens of thousands of transistors on a desktop workstation.

In this paper, we present a hierarchical reliability-driven CAD system for the design of electromigration resistant circuits.The top of the hierarchy aims at quickly identifying those critical interconnects with potential electromigration reliability problems.Then the detailed electromigration analysis of critical interconnects is carried out by an accurate and computationally ecient simulation tool (iTEM).This top-down approach provides a feasible solution to the complicated electromigration diagnosis problem.

In this paper, a new thermal simulator is developed to predict the steady-state and transient temperatures inside a VLSI chip subjected to heating by single or multiple heat sources. It uses a mixed 3D finite-difference and 1D analogous thermal circuit method, taking into account any combination of boundary conditions, shape of heat sources, and packaging. An analytical method is also presented and compared to the numerical method. With this tool, the chip temperature can be predicted accurately to provide design guidelines for VLSI module placement and chip packaging.