Teaching in the area of embedded systems is challenging because both software and hardware development must be considered in an integrated manner. The experience gained through the practical hardware-related implementation of prototypes cannot simply be replaced by simulations. The question is, however, how can students gain as much practical experience as possible while taking into account real laboratory constraints? We present an approach that allows students to gain practical experience via virtual access to laboratory setups, which allows them to work in groups remotely and then continue their work in the labs, providing a similar experience as under normal lab conditions. For educators, we introduce a flexible environment that can be adopted to specialized embedded courses due to the used components and methodology of the ADDIE teaching model.

Digital Twin (DT) is a core concept in the digitalization process in the Industry 4.0 and upcoming innovations such as Industry 5.0 and Metaverse. This digitalization can result in a huge amount of data that has not been collected before and now can help to understand and optimize processes and products. However, an important challenge is to really understand what the data can mean and then find out new information and knowledge that can be used for further optimizations. Therefore, it is important to have the virtual representations that the DT proposes as close as possible to the real-world application in a way that it can be understood in the same way by different people and systems. In this context, semantics annotations can be used to organize data by inserting knowledge into the model and providing a common understanding of a specific concept. This paper proposes a methodology for creating semantic digital twin models using the well-known tool called Node-RED. A sequence of steps is described that covers data acquisition, semantics annotations to this incoming data, assets modeling with their relationships which generates a graph of nodes and connections that is saved into a graph database. To be able to realize such a model, 7 so-called nodes have been developed for Node-RED. Finally, a use case has been implemented to demonstrate the application of the proposed methodology.

Assessing the overall accuracy of deep learning classifier is not a sufficient criterion to argue for safety of classification based functions in highly automated driving. The causes of deviation from the intended functionality must also be rigorously assessed. In context of functions related to image classification, one of the causes can be the failure to take into account during implementation the classifier's vulnerability to misclassification due to high similarity between the target classes. In this paper, we emphasize that while developing the safety assurance case for such functions, the argumentation over the appropriate implementation of the functionality must also address the vulnerability to misclassification due to class similarities. Using the traffic sign classification function as our case study, we propose to aid the development of its argumentation by: (a) conducting a systematic investigation of the similarity between the target classes, (b) assigning a corresponding classifier vulnerability rating to every possible misclassification, and (c) ensuring that the claims against the misclassifications that induce higher risk (scored on the basis of vulnerability and severity) are supported with more compelling sub-goals and evidences as compared to the claims against misclassifications that induce lower risk.

─Smart City is one area of application for the Internet of Things (IoT) and it has been attracting attention from both academia and industry. Cities will be composed by autonomous parts that communicate and provide services to each other. For instance, cars (autonomous or not) may be seen as a service that transports people from one point to another. Interactions between users and these kinds of services will grow, making it necessary to have digitization of all these parts of the Smart City. The Digital Twin (DT) concept proposes that real-world assets have a virtual representation connecting the physical world with the cyber world. This allows to track the whole life-cycle of this object as well as perform simulations with current or previously stored data. In this context, this work proposes the use of Digital Twin for enabling and supporting car-as-a-service (CaaS). A case study has been developed to demonstrate the modeling and the deployment of the Digital Twin, highlighting how this concept can be one of the key enablers for CaaS.

The digital twin (DT) is a virtual representation of a physical object, which has been proposed as one of the key concepts for Industry 4.0. The DT provides a virtual representation of products along their lifecycle that enables the prediction and optimization of the behavior of a production system and its components. A methodology design using model-driven engineering (MDE) is proposed that strives toward being both flexible and generic. This approach is presented at two levels: first, a DT is modeled as a composition of basic components that provide basic functionalities, such as identification, storage, communication, security, data management, human-machine interface (HMI), and simulation; second, an aggregated DT is defined as a hierarchical composition of other DTs. A generic reference architecture based on these concepts and a concrete implementation methodology are proposed using AutomationML. This methodology follows an MDE approach that supports most of the DT features currently proposed in the literature. A case study has been developed, the proposed ideas are being evaluated with industrial case studies, and some of the preliminary results are described in this article. With the case study, it is possible to verify that the proposed methodology supports the creation and the deployment process of a DT.

When developing Real-Time and Embedded Systems (RTES), different types of constraints should be considered in specification, modeling, architectural design and system implementation. In most cases, these constraints describe timing, precedence or resource restriction. Correct description and evaluation of these complex information along of RTES design are directly related to their reliability, safety and quality. In this research, a methodology to describe real-time and embedded information in requirements, functional, logical and technical viewpoints is briefly presented, as well as an approach to analyze the annotated constraints. MARTE constraints have been consistently applied in designing models and implemented at lower abstraction models. Here, pseudo automated generation of timing, precedence and resources constraints is performed from the graphical models to the final source code models. Therefore, the proposed approach has a great value to RTES design once it has traced constraints along of the architectural design and it also presents a manner to check if constraints are being reached in accordance with early design description.

Architectural design of Real-Time and Embedded Systems must describe the system components (software and hardware) in a common and comprehensible manner to be understandable to several stakeholders involved in the development process. This article explores the combined adoption of a well-recognized methodology to activities of architectural system design, with the MARTE profile, considering non-functional annotations in model elements. The proposed approach aims to define a general and appropriate architectural viewpoint to the real-time and embedded domain. MARTE profile and SPES methodology are employed in modeling strategies in order to explore the requirements, services and systems components. In this paper, a case study in the automotive system domain is performed and the architectural viewpoints are able to represent functional and non-functional requirements, performance and temporal restrictions in the field of automotive systems at different levels of detail and abstraction.

Development of Real-Time and Embedded Systems (RTES) involves a number of complex activities performed by a diversity of stakeholders. In most cases, RTES requires a number of different physical and logical components with numerous functional and non-functional constraints. Therefore, it is essential to ensure the representation, specification and analysis of quality activities of these systems since the early design activities. SPES (Software Platform Embedded Systems) methodology has been considered to describe a framework to develop RTES, but it does not specify directly how and which modeling languages should be adopted. Thus, this research adopts SPES guidelines and applies SysML and MARTE profiles to create models in the architectural viewpoints, while it highlights functional properties and different non-functional constraints of the system. A formalization of design viewpoints is presented in order to contribute to quantitative measurement to describe an analysis of the design complexity since the initial design activities. As contributions of this paper, it can be highlighted a proposal to formalize the RTES design activities (viewpoints), a measurement of the system design complexity since the initial design activities (in accordance with the design activities) and, also, the definition of a formalized manner to analyse RTES complexity without the interference of user external knowledge.

Real-time and embedded systems (RTES) encompass a variety of embedded and real-time properties and requirements which defines them. Timing behavior of RTES physical and logical subsystems is as important as their functional behavior. These systems must define, in addition to their functional properties, the control of several peripheral components, of their constraints, communication interfaces and temporal and non-functional requirements. Understanding the representation and treatment of several properties of real-time and embedded systems has direct influence in their development, reliability and safety. Therefore, it is pertinent to analyze the properties that represent this domain and to provide strategies for a complete definition of model elements'. This paper aims to provide guidelines for comprehension, application and possible adoption of the UML MARTE (Modelling and Analysis of RealTime and Embedded Systems) profile in specification, modeling and design of real-time and embedded properties of a system. The proposed design strategy is applied to a case study, in the domain of intelligent automation systems, in order to direct the adoption of the constructors of MARTE profile in other development contexts and to describe the semantics and syntax of these builders to strengthen their comprehensibility.

The increasing complexity of contemporary embedded computing systems requires the use of selfmanagement in order to handle unforeseen changes in both hardware and application environments (i.e., hardware/software defects, resource changes, and non-continual feature usage).Moreover, often these systems are distributed, running on processor architectures with multiple cores, which may require self-organization to ensure efficiency and reliability.Real-time properties are another key issue in many complex systems.Adaptive and self-organized properties extent the area of operations and improves the efficiency of the system resources at the cost to introduce additional complexity, overhead, and resource requirements.Consequently, real-time adaptive systems must be careful analyzed, designed, and built taken into account the right tradeoffs between flexibility and complexity, while accomplishing time-constrains.The combination of the flexibility and uncertain behavior of self-organizing systems with timepredictability is a grand challenge.Therefore, substantial research has been done in the last years to address the so-called Self-X features (e.g., self-configuration, self-optimization, self-adaptation, selfhealing, and self-protection).This fact has as resutl that self-organizing computing systems become an established research nowadays as they promise to handle the increasing complexity resulting from highly distributed systems and ubiquitous applications.In addition, real-time properties are required in many areas (such as cyber physical systems) self-organizing computing systems are dealing with.Combining the flexible and and uncertain behavior of self-organizing systems with time-predictability necessary for real-time systems is a grand challenge.The Workshop on Self-Organizing Real-Time Systems (SORT) is specifically dedicated to research on adaptive real-time systems.SORT started 2014 as a workshop attached at International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC).The purpose of this workshop is to provide an open forum to discuss new and ongoing research that is centered on the idea of adaptability in real-time systems.The target audience includes researchers from academia, tool vendors, system suppliers, and users in industry who are interested in the all aspects of the topics mentioned below.This special issue of Concurrency and Computation: Practice and Experience contains four invited papers from the SORT 2014 workshop that has been expanded and carefully peer reviewed.The first paper, titled An Artificial DNA for Self-Descripting and Self-Building Embedded Real-Time Systems [1], Uwe Brinkschulte proposes an approach to use an artificial DNA-based approach for embedded real-time and distributed systems.This kind of systems is growing more and more complex because of the increasing chip integration density, larger number of chips in distributed applications and demanding application fields (e.g., in cars and in households).Bio-inspired techniques like self-organization are a key feature to handle this complexity.Because many embedded systems can be composed from a limited number of basic elements, the structure and parameters of such systems can be stored in a compact way representing an artificial DNA deposited in each computation node.This leads to a self-describing system.Based on the DNA, the self-organization mechanisms can build the system autonomously providing a selfbuilding system.System repair and optimization at runtime are also possible, leading to higher robustness, dependability, and flexibility.Autonomous adaptation in self-adapting embedded real-time systems introduces novel risks as it may lead to unforeseen system behavior.An anomaly detection framework integrated in a real-time operating system can ease the identification of such suspicious novel behavior and, thereby, offers the potential to enhance the reliability of the considered self-x system.However, anomaly detection is based on knowledge about normal behavior.When dealing with self-reconfiguring applications, normal behavior changes.Hence, knowledge base requires adaptation or even reconstruction at runtime.The stringent restrictions of real-time systems considering runtime and memory consumption make this task to a really challenging problem.

Fault-injection is a commonly used method for testing safety-relevant embedded systems. Especially after the introduction of the ISO 26262 the importance of this technique has gained attention in the automotive domain to test the proper implementation of safety concepts. To enable meaningful tests, the possible random hardware faults need to be aligned in early stages of the development process between the hardware and software developers. Since it is difficult to reason that a system nominal behavior is not affected by the injected fault-code, we aim at an automatic injection of faults into the software units using an AUTOSAR tool-chain. An extension in the AUTOSAR design tool is proposed in order to capture fault definitions that shall be used to automatically create trigger-able defects in the behavioral models designed with SIMULINK/Targetlink. As first results, it is demonstrated how to integrate faults in Targetlink to be able to use AUTOSAR simulation environments without any further changes to perform fault-injection tests. Furthermore, automatically generated test-vectors from requirements are used to trigger the fault injection at runnable level.

The analysis of real-time properties is crucial in safety critical areas. Systems have to work in a timely manner to offer correct services. The analysis of timing properties is particularly difficult for distributed systems when complex interferences between individual tasks can occur. Considering only critical instances, as analytic approaches do, may deliver pessimistic results leading to higher production costs. In previous works we introduced a state-based approach to validate task-and end-to-end deadlines for distributed systems. To improve scalability and reduce the analysis time, the approach computes the state spaces of the individual resources in a compositional fashion. For this, abstraction and composition operations were defined to remove those parts of the inputs of resources which have no influence on the response times of the allocated tasks. In this work, a new abstraction technique is introduced for scenarios where event bursts occur. Further, we extend our approach for systems with cyclic dependencies among the resources. We evaluate our approach on a set of example scenarios and compare the results with the state-of-the-art tool Uppaal.

The design and evolution of today's embedded systems face an increasing complexity both in the applications and in the platforms that support them. The use of complex platforms means that the engineers need to make non-trivial decisions during the design phase including optimized allocation, binding and scheduling. This situation creates a need for better ways to manage project complexity, and Model Driven Engineering is a possible solution. In this work, we propose an extension of a Model Driven Engineering methodology (i.e. HIPAO) to help manage complexity, which includes an automated Design Space Exploration phase that uses Genetic Algorithms to find the best hardware/software partitioning for a given application. We apply the HIPAO methodology to a case study of an autonomous industrial inspection system.

Modular verification approaches have recently gained attention to enable cost efficient handling of changes in safety critical embedded systems. First results in this field are based on formal languages and iterative change processes to analyze the neighboring design elements of the change and thereby determine the effects of the change and possible inconsistencies. The alternative, being mostly applied in practice, is the complete re-verification of modules or even the whole product. In this paper we present simulation results comparing the effectiveness of both approaches by analyzing their effort of re-validation to regain a consistent set of requirements and implementations. As modular re-verification strategies execute only the needed analyzes, the effort progresses linearly with the number of necessary changes within the system. Consequently, we find that for a small number of changes this approach presents a huge saving in contrast to the commonly used approach of complete re-verification. Surprisingly, the critical portion of changes over the system size at which both approaches perform equally well is relatively small.

Multi-rotor Unmanned Aerial Vehicles (UAVs) are interesting for commercial as well as for private use. Simple tasks like aerial photography are well known, but nowadays new scenarios, like on-board video processing or complex sensor data processing, are gaining in importance. These scenarios require high-performance on-board processing which is not available in most of today's avionics architectures for civilian multi-rotor systems. Due to the limited installation space and weight requirements, the usage of highly integrated Multi-Processor System on Chips (MPSoCs), capable to implement real-time critical flight control algorithms and compute intensive custom payload functions is appealing. This paper presents fundamental requirements on the architecture and flight control algorithms of existing autonomously flying commercial multi-rotor UAVs. On this basis a new approach for an avionics architecture using the Xilinx ZYNQ (MPSoC) is proposed. In combination with the presentation of the proposed architecture new challenges will be discussed that result from the integration of mixed-critical applications on a single chip.

The analysis of real-time properties is crucial in safety critical areas, and is particularly difficult for distributed systems as complex interferences between tasks of different priorities can occur. In previous works we have introduced a state-based analysis approach to validate end-to-end deadlines for distributed systems, where the state spaces of all resources, such as processors and buses, are computed in a compositional fashion. For this, abstraction and composition operations were defined to adequately handle task and resource dependencies. During the design process of a system changes occur typically on both the specification and implementation level, such that already performed analyses of the system have to be repeated. In this work, we define a methodology to adequately handle such changes and to determine the minimal part of the affected architecture. For this, we define an appropriate refinement relation between state spaces of the resources. We use contracts to further reduce the re-validation effort. This check takes place at a higher design level, where only the specification is considered.

The timing predictability of embedded systems with hard real-time requirements is fundamental for guaranteeing their safe usage. With the emergence of multicore platforms this task became very challenging. In this paper, a model-checking based approach will be described which allows us to guarantee timing bounds of multiple Synchronous Data Flow Graphs (SDFG) running on shared-bus multicore architectures. Our approach utilizes Timed Automata (TA) as a common semantic model to represent software components (SDF actors) and hardware components of the multicore platform. These TA are explored using the UPPAAL model-checker for providing the timing guarantees. Our approach shows a significant precision improvement compared with the worst-case bounds estimated based on maximal delay for every bus access. Furthermore, scalability is examined to demonstrate analysis feasibility for small parallel systems.

In this work we address evolving systems, which are basically collaborative and distributed systems building up a larger scale system of system (SoS). These systems are able to adapt the current architecture to some changes in the environment. Constituent systems of a SoS, which represent the basic elements of our modeling approach, operate with different degrees of freedom and as a result the self-adaptation and cooperation between a set of constituent systems is driven by local needs. Based on our former work [11], we propose a well-defined modelling approach for SoS capturing both static and dynamic aspects. The aim is to address on the one hand the required flexibility to adapt the systems during run-time, and on the other hand to guarantee that the SoS reacts still in a safe manner. For this, we will use the contract paradigm for both the specification of legal configurations of the SoS, and to specify the dynamicity model, describing how the SoS architecture can change during run-time. Further, we depict how to adapt a system level analysis technique in order to check the dynamicity model against the invariants of the SoS. With this, we are able to determine, whether the SoS can reach some critical configurations. This enables us to modify the dynamicity model in an adequate manner.

With the accelerating pervasiveness of multi-core platforms in the embedded domains and the on-going need for more computational power and increased integration, multi-core scheduling for real-time and mixed-critical applications is an active research topic. In this paper, we give an overview on the history and the current state-of-the-art on multi-core real-time scheduling. A special focus is put on shared resource access protocols and hierarchical scheduling approaches, both of which are increasingly important due to the higher spatial integration and stronger coupling between the different subsystems, both on the application and on the multi-core architectural level. Moreover, hierarchical scheduling is a promising approach in the area of mixed-criticality systems to enable composability and segregation, which is needed to cope with the complexity of such systems. This survey will be of interest to researchers and practitioners in the field of real-time scheduling for multi-core systems.

Today, using dynamic partial reconfiguration of FPGAs leads to a longer and less predictable design cycle. To improve this, we developed a modelling, simulation, and synthesis framework for partial reconfiguration, named OSSS+R. It reduces design time and hides some of the complexity. The tool PART-E integrates the results into the Xilinx early access partial reconfiguration (EAPR) flow. It eases floorplanning, bus macro instantiation, and bitstream generation. We show OSSS+R modelling, simulation and Part-E in a hands-on fashion. Synthesis to VHDL is demonstrated, too.

When reconfigurable devices are used in modern embedded systems and their capability to adapt to changing application requirements becomes an issue, comprehensive modeling and design methods are required. Such methods must respect the whole range of functionality of the reconfigurable fabrics. In particular, the heterogeneity and reconfiguration delay of modern FPGAs are important details. Comprehensive methods to exploit these characteristics within the integrated design of embedded systems are still not available. In this paper, we introduce a synthesis methodology for reconfigurable systems that respects the specific requirements of run-time reconfiguration. The methodology bases on profound concepts, and expands known notations and model techniques.

UML 2.0 provides a rich set of diagrams for systems documentation and specification. Much effort has been undertaken to employ different aspects of UML for multiple domains, mainly in the area of software systems. Considering the area of electronic design automation, however, we currently see only very few approaches which investigate UML for hardware design and hardware/software co-design. We present an approach for executable UML closing the gap from system specification to its model-based execution on reconfigurable hardware. For this purpose, we present our abstract execution platform (AEP), which is based on a virtual machine running an executable UML subset for embedded software and reconfigurable hardware. This subset combines UML 2.0 classes, state-machines and sequence diagrams for a complete system specification. We describe how these binary encoded UML specifications can be directly executed and give the implementation of such a virtual machine on a Virtex II FPGA. Finally, we present evaluation results comparing the AEP implementation with C code on a C167 microcontroller.

The paper introduces an approach for realizing high-level Petri net-models in SystemC. The presented approach contributes to an existing methodology for the Petri net-based design of distributed embedded real-time systems. It is intended to be a vehicle for realizing Petri net-components in hardware. The paper describes the use of standard SystemC language constructs to realize the firing of a high-level Petri net, which is assumed to be separated into partitions. The execution includes for instance the execution of single transitions, the handling of conflicting transitions, the realization of transition delays and the communication between Petri net-components realized in different partitions. Besides techniques for realizing these mechanisms, the integration of the code generation into the overall design flow is discussed.

The structure of Internet applications and scenarios is changing rapidly today. This offers new potential for established technologies and methods to expand their area of application. New technologies encourage new methodologies to design processes and business-to-business applications. The application of such new advancements should be extended into the domain of the electronic design automation (EDA) industry. In this paper we present an approach to use webservices in the field of embedded system design.