Integrity assurance of configuration data has a significant impact on microcontroller-based systems reliability. This is especially true when running applications driven by events which behavior is tightly coupled to this kind of data. This work proposes a new hybrid technique that combines hardware and software resources for detecting and recovering soft-errors in system configuration data. Our approach is based on the utilization of a common built-in microcontroller resource (timer) that works jointly with a software-based technique, which is responsible to periodically refresh the configuration data. The experiments demonstrate that non-destructive single event effects can be effectively mitigated with reduced overheads. Results show an important increase in fault coverage for SEUs and SETs, about one order of magnitude.

The estimate of the probability density function or probability mass function of an unknown stochastic process is a very important preliminary step for any further elaboration. Most of the traditional approaches to this problem perform a preliminary choice of a parametric mathematical model of the function to estimate and a subsequent fitting on its parameters. To this aim some a-priori knowledge and/or assumptions on the phenomenon under consideration are needed. In this paper an alternative approach is proposed, which does not require any assumption on the available data, as it extracts the probability density function from the output of a neural network, that is trained with a suitable database including the original data and some ad hoc created data with known distribution. The results of the tests performed on synthetic and industrial databases are described and discussed in the paper.

Data preprocessing is a main step in data mining because real data can be corrupted for different causes and high performance data mining systems require high quality data. When a database is used for training a neural network, a fuzzy system or a ne

This paper describes an approach to the placement of self-timed circuits onto commercial FPGAs, using only conventional synchronous tools available on the market. Different parts of the design are constrained in order to maintain the timing relationship required for guaranteeing the correct circuit functionality and to keep the wiring influence on system delays bounded and fixed across the different iterations. This work is part of the extension to the CodeSimulink co-design environment we made in order to allow the synthesis of asynchronous circuits from Simulink specifications.

When designing a neural or fuzzy system, a careful preprocessing of the database is of utmost importance in order to produce a trustable system. In function approximation applications, when a functional relationship between input and output variables is supposed to exist, the presence of data where the similar set of input variables is associated to very different values of the output is not always beneficial for the final system to design. A method is presented which can be used to detect anomalous data, namely non-coherent associations between input and output patterns. This technique, by mean of a comparison between two distance matrix associated to the input and output patterns, is able to detect elements in a dataset, where similar values of input variables are associated to quite different output values. A numerical example and a more complex application in the pre-processing of data coming from an industrial database were presented.

The paper analyses the issues behind strategies optimization of an existing automated warehouse for the steelmaking industry. Genetic algorithms are employed to this purpose by deriving a custom chromosome structure as well as ad-hoc crossover and mutation operators. A comparison between three different solutions able to deal with multiobjective optimization are presented: the first approach is based on a common linear weighting function that combines different objectives; in the second, a fuzzy system is used to aggregate objective functions, while in the last the strength Pareto genetic algorithm is applied in order to exploit a real multiobjective optimization. These three approaches are described and results are presented in order to highlight benefits and pitfalls of each technique.

This paper analyzes the stage of maturity that neurofuzzy systems (and soft computing in general) have recently reached and tackles the several reasons why they have not yet reached a widespread acceptance in industrial and agronomic applications, despite the good performance they can offer with a reduced design effort.

A fully digital test stimuli generation and on-chip specifications evaluation for cheap, fast, though accurate testing of high resolution ΣΔ ADCs are here presented. Simulations and measurements showed a discrimination threshold on specification parameters up to -90 dBc. The proposed method helps reduce the cost of ADC production test, to extend test coverage and to enable built-in self-test and test-based self-calibration.

Asynchronous design has become more and more popularin last years. Many tools and design methodologies have been developed for this kind of circuits. Unfortunately only few of them are focused on their implementation onto FPGAs. Nowadays FPGAs are widespread in many applications and they have enough complexity to allow prototyping also complex designs. For this reason this paper is focused on the implementation of asynchronous-specific blocks on programmable devices using conventional tools and flows. It offers solutions for implementing Muller C elements and delay chains onto FPGAs avoiding unwanted behavior given by the synthesis and the fitting phases. This paper also introduces the solution adopted in our co-design environment to automatically generate delay chains used to single-rail implementation of asynchronous circuits. This is a part of our project which aims at developing a complete framework for producing asynchronous circuits from Simulink models.

This paper presents the architecture of a small university satellite that we have developed. The main design criteria were low cost and fault tolerance, which have been achieved by using Commercial Off The Shelf components and by replicating all critical functions, while monitoring the state of the system for failures. The focus of the paper is on overall organization, design partitioning and details of the actual hardware. We show that the development of a low-cost satellite is feasible with a very limited budget.

This paper presents a synthesis tool for the automatic translation and optimization of bioinspired vision models into a FPL implementation. The software allows functional simulation and high level specification of the model, and produces a data-flow model using VHDL, which is synthesizable with different lower-level synthesis tools and for various FPGA technologies. The proposed design platform extends the features of the codesign environment CodeSimulink for implementing visual processing systems, starting from purely functional specifications. An optimization strategy based on the calculation of the Pareto front is also introduced to perform a multi-objective minimization of both, the circuit area and the root mean square of the computation error. Performance measurements for the FPL implementation of an example retina-like vision model on a FPGA-based PCI board are provided

This paper presents an annotated overview of existing hardware implementations of artificial neural and fuzzy systems and points out limitations, advantages, and drawbacks of analog, digital, pulse stream (spiking), and other implementation techniques. We analyze hardware performance parameters and tradeoffs, and the bottlenecks which are intrinsic in several implementation methodologies. The constraints posed by hardware technologies onto algorithms and performance are also described. The results of the analyses proposed lead to the use of hardware/software codesign, as a means of exploiting the best from both hardware and software techniques. Hardware/software codesign appears, at present, the most promising research area concerning the implementation of neuro-fuzzy systems (not including bioinspired systems, which are out of the scope of this work), as it allows the fast design of complex systems with the highest performance/cost ratio.

This paper describes a design flow for data-dominated embedded systems. We use The Mathworks ’ Simulink environment for functional specification and algorithmic analysis. We developed a library of Simulink blocks, each parameterized by design choices such as implementation (software, analog or digital hardware, ) and numerical accuracy (resolution, S/N ratio). Each block is equipped with empirical models for cost (code size, chip area) and performance (timing, energy), based on surface fitting from actual measurements. We also developed an analysis toolbox that quickly evaluates algorithm and parameter choices performed by the designer, and presents the results for fast feedback. The chosen block netlist is then ready for implementation, by using a customization of The Mathworks ’ Real Time Workshop to generate a VHDL netlist for FPGA implementation, as well as embedded software for DSP implementation. 1.

Presents Beatrix, a system for off-line recognition of handwritten sentences. The system consists of four subsystems: the first pre-processes the input bitmap and splits each sentence into words; the second integrates neural and fuzzy logic techniques for individual character recognition; the third carries out a lexical and grammatical analysis of the recognised text; and the fourth uses the words recognised with a high confidence value to re-train the second subsystem on the specific handwriting. The analysis performed by the third subsystem produces hypotheses about words and sentences in order to correct errors made by the second subsystem. The fourth subsystem allows the system to self-adapt to the specific handwriting under examination; therefore, the system possesses the properties of both writer-independent and writer-dependent systems.

We propose a semi-automatic HW/SW codesign flow for low-power and low-cost Neuro-Fuzzy embedded systems. Applications range from fast prototyping of embedded systems to high-speed simulation of Simulink models and rapid design of Neuro-Fuzzy devices. The proposed codesign flow works with different technologies and architectures (namely, software, digital and analog). We have used The Mathworks' Simulink environment for functional specification and for analysis of performance criteria such as timing (latency and throughput), power dissipation, size and cost. The proposed flow can exploit trade-offs between SW and HW as well as between digital and analog implementations, and it can generate, respectively, the C, VHDL and SKILL codes of the selected architectures.

This paper analyzes several commonly used soft computing paradigms (neural and wavelet networks and fuzzy systems, Bayesian classifiers, fuzzy partitions, etc.) and tries to outline similarities and differences among each other. These are exploited to produce the weighted radial basis functions paradigm which may act as a neuro-fuzzy unification paradigm. Training rules (both supervised and unsupervised) are also unified by the proposed algorithm. Analyzing differences and similarities among existing paradigms helps to understand that many soft computing paradigms are very similar to each other and can be grouped in just two major classes. The many reasons to unify soft computing paradigms are also shown in the paper. A conversion method is presented to convert perceptrons, radial basis functions, wavelet networks, and fuzzy systems from each other.

Artificial neural networks (NNs) and fuzzy systems are highly parallel structures that consist of a large number of fully interconnected elementary nonlinear units (called neurons). We present a digital hardware implementation of NNs combined with a host computer (DSP systems, PCs, etc.) resulting in a powerful system used in different applications. The NNs process most of the tasks, while the host performs signal pre-processing and learning algorithms. In some control applications the host also tracks some discrete states of the plant by implementing a finite state automata and/or verifying plant safety boundaries operations. The tight link with the host allows the NN hardware to be very simple since several operations related with the NNs (learning, weights initialization, etc.) can be performed by the host computer. The board can be used to implement intelligent control paradigms mixing neuro-fuzzy algorithms with finite state automata and/or digital control algorithms.

The paper describes the architecture of an image coprocessor based on a linear array of elementary processors. The system has been designed for real-time vision applications and embeds a direct I/O interface to a camera device. The instruction set of the elementary processors is based on morphological match operators on a reduced 5/spl times/5 neighborhood. Two additional communication mechanisms, one fixed and one programmable, provide both global and multiple communication channels among processing elements which are not directly connected.>

The PAPRICA project started in 1988 as an experimental VLSI architecture devoted to the efficient computation of data with two-dimensional structure. The main goal of the project is to develop a subsystem that could operate as an attached processing unit to a standard workstation and in perspective as a specialized processing module in dedicated systems devoted to low level image analysis, cellular neural networks emulation, DRC algorithms. The architecture has been extensively used for basic low level image analysis tasks up to optical flow computation and feature tracking, showing encouraging performance even in the first prototype version. The authors discuss the actual implementation and present a critical analysis of the project, allowing to identify some crucial points of PAPRICA design (and of array processors in general) that must be carefully considered in the case of redesign.>

This paper describes an existing silicon implementation of an artificial neural system based on coherent pulse width and edge modulation techniques. A chip set with different neural functions has been conceived, manufactured and tested. Neural circuits have been optimized for lowest computation energy and highest reconfigurability. The main device is a 32 x 32 synaptic array consuming 10 mW of power at 140 MCPS. Synapsis size is about 7.200 microns 2 using a standard 1.5 microns CMOS technology. The problem of interfacing robotic sensors and actuators is addressed: voltage, current and resistance-based sensors are considered for the measurement of physical quantities such as temperature, pressure, strain, etc. Low resolution imaging sensors for robotic vision are also considered.

The effects of silicon implementation on the backpropagation learning rule in artificial neural systems are examined. The effects on learning performance of limited weight resolution, range limitations, and the steepness of the activation function are considered. A minimum resolution of about 20/22 bits is generally required, but this figure can be reduced to about 14/15 bits by properly choosing the learning parameter eta which attains good performance in presence of limited resolution. This performance can be further improved by using a modified batch backpropagation rule. Theoretical analysis is compared with ad-hoc simulations and results are discussed in detail.>