Traditionally, the placement and routing stages of a physical design are performed separately. Because of the additional complexities arising in advanced technology nodes, they have become more interdependent. Therefore, creating efficient cooperation between the routing and placement steps has become an important topic in Electronic Design Automation (EDA). In this article, a framework that allows cooperation between routing and placement is proposed. The main objective of the proposed framework is to improve the detailed routing solution by combining routing and placement. The core of this framework is the Cooperation between Routing and Placement (CRP2.0) 1 engine including techniques to combine routing and placement. The key contributions of CRP2.0 include an Integer Linear Programming (ILP)-based Detailed Placement (ILP-DP), net classification, and two Cost and Net Caching techniques. The efficacy of the proposed framework is evaluated on the official ACM/IEEE International Symposium on Physical Design (ISPD) 2018 and 2019 contest benchmarks. In this article, we show that by using the Cost Caching technique, the global routing runtime compared with state-of-the-art algorithms was reduced by 28.56%, on average. Moreover, numerical results show that when working with advanced technology nodes, the proposed framework can improve the detailed routing score by an average of 0.3% while only moving 0.7% of the cells, on average. The proposed engine can be employed as an add-on to the physical design flow between the global routing and detailed routing steps.

Placement and Routing (P&R) are two main steps of the physical design flow implementation. Traditionally, because of their complexity, these two steps are performed separately. But the implementation of the physical design in advanced technology nodes shows that the performance of these two steps is tied to each other. Therefore, creating efficient co-operation between the routing and placement steps has become a hot topic in Electronic Design Automation (EDA). In this work, to achieve an efficient collaboration between the routing and placement engines, an iterative replacement and rerouting framework facilitated with an Integer Linear Programming (ILP)-based legalizer is proposed and tested on the ACM/IEEE International Symposium on Physical Design (ISPD) 2018 contest's benchmarks. Numerical results show that the proposed framework can improve detailed routing vias and wirelength by 2.06% and 0.14% on average in a reasonable runtime without adding new Design Rule Violations (DRVs). The proposed framework can be considered as an add-on to the physical design flow between global routing and detailed routing.

The legalization step is performed after global placement where wire length and routability are optimized or during timing optimization where buffer insertion or gate sizing are applied to meet timing requirements. Therefore, an ideal legalization approach must preserve the quality of the input placement in terms of routability, wire length, and timing constraints. These requirements indirectly impose maximum and average cell movement constraints during legalization. In addition, the legalization step should effectively manage white space availability with a highly efficient runtime in order to be used in an iterative process such as timing optimization. In this article, a robust and fast legalization method called Eh?Legalizer for standard-cell placement is presented. Eh?Legalizer legalizes input placements while minimizing the maximum and average cell movements using a highly efficient novel network flow-based approach. In contrast to the traditional network flow-based legalizers, areas with high cell utilizations are effectively legalized by finding several candidate paths and there is no need for a post-process step. The experimental results conducted on several benchmarks show that Eh?Legalizer results in 2.5 times and 3.3 times less the maximum and average cell movement, respectively, while its runtime is significantly (18×) lower compared to traditional legalizers. In addition, the experimental results illustrate the scalability and robustness of Eh?Legalizer with respect to the floorplan complexity. Finally, the detailed-routing results show detailed-routing violations are reduced on average by 23% when Eh?Legalizer is used to generate legal solutions.

The placement problem has become more complex and challenging due to a wide variety of complicated constraints imposed by modern process technologies. Some of the most challenging constraints and objectives were highlighted during the most recent ACM/IEEE International Symposium on Physical Design (ISPD) contests. In this article, the framework of Eh?Placer and its developed algorithms are elaborated, with the main focus on modern technology constraints and runtime. The technology constraints considered as part of Eh?Placer are fence region, target density, and detailed routability constraints. We present a complete description on how these constraints are considered in different stages of Eh?Placer. The results obtained from the contests indicate that Eh?Placer is able to efficiently handle modern technology constraints and ranks highly among top academic placement tools.

The placement problem has become challenging due to a variety of complicated constraints imposed by modern process technologies. Some of the most challenging constraints were highlighted during the ISPD 2015 placement contest and include fence region and target density constraints; these constraints are in addition to those issues that affect detailed routability such as pin shorts, pin access problems and cell spacing issues. These constraints not only make cell placement more difficult, but can impact the placement objectives such as wire length, routability and so forth. In this paper, we present a comprehensive technique to address fence region constraints in global placement and legalization while still considering detailed-routing issues. We combine concepts from image processing such as region coloring with parallel programming to efficiently deal with fence regions. We also introduce a heuristic method to adjust target densities while avoiding adverse effects on the quality of global routability. Numerical results using both the released and hidden benchmarks from the ISPD 2015 placement contest demonstrate the efficacy of our proposed techniques.

In this paper, we present and analyze four efficient models that produce significantly improved results by optimizing conflicting power and skew objectives in the clock network buffer sizing problem. Each model is in geometric programming format and has certain advantages, such as maximum reduction in power, robustness to process variation, and striking a balance between skew and power optimization. The buffer sizing problem is formulated as a geometric programming problem to provide globally optimal solutions to the four models. We also show that a geometric programming multiobjective model can be used to optimize both power and skew without requiring any tuning from a designer. The presented self-tuning multiobjective formulation not only provides optimal solutions for buffer sizes, but also finds the tuning parameters that result in overall combined reduction in power and skew without loss of convexity. The effectiveness of the models are illustrated on several publicly available benchmarks. The models provide on average 40% to 60% improvement in power while reducing skew in several cases. We have also proposed a smart heuristic for discretization of the continuous geometric programming solution that preserves skew and power. Finally, we provide a guideline for designers to decide which one of the proposed models is the most appropriate for their needs.

Most engineering problems involve optimizing different and competing objectives. To solve multi-objective problems, normally a weighted sum of the objectives is optimized. However, how the weights are assigned can greatly affect the outcome. Therefore, many designers have to resort to producing the Pareto surface - a time-consuming procedure. In this paper, we propose a framework for solving multi-objective geometric programming problems where weights in the objective are optimally calculated during the optimization problem without having to produce the Pareto surface. It is shown that the proposed self-tuning multi-objective framework can be applied to geometric programming gate sizing problems. Then, the efficacy of the proposed framework is proven using the clock network buffer sizing problem as an application. The problem is first formulated as a geometric programming (GP) problem with the objectives of reducing power, skew, and slew. The problem is solved using ISPD09 circuits. The power, skew and slew of the optimized networks are calculated using ngspice. The results show on average 52% reduction in power and 28% reduction in skew compared to the original networks. The self-tuning multi-objective solution is shown superior to any single objective solution with no impact on runtime.

Minimizing power and skew for clock networks are critical and difficult tasks which can be greatly affected by buffer sizing. However, buffer sizing is a non-linear problem and most existing algorithms are heuristics that fail to obtain a global minimum. In addition, existing buffer sizing solutions do not usually consider manufacturing variations. Any design made without considering variation can fail to meet design constraints after manufacturing. In this paper, first we proposed an efficient optimization scheme based on geometric programming (GP) for buffer sizing of clock networks. Then, we extended the GP formulation to consider process variations in the buffer sizes using robust optimization (RO). The resultant variation-aware network is examined with SPICE and shown to be superior in terms of robustness to variations while decreasing area, power and average skew.

A robust identification algorithm has been developed for linear, time-invariant, multiple-input single-output systems, with an emphasis on how this algorithm can be used to estimate the dynamic relationship between a set of neural recordings and related physiological signals. The identification algorithm provides a decomposition of the system output such that each component is uniquely attributable to a specific input signal, and then reduces the complexity of the estimation problem by discarding those input signals that are deemed to be insignificant. Numerical difficulties due to limited input bandwidth and correlations among the inputs are addressed using a robust estimation technique based on singular value decomposition. The algorithm has been evaluated on both simulated and experimental data. The latter involved estimating the relationship between up to 40 simultaneously recorded motor cortical signals and peripheral electromyograms (EMGs) from four upper limb muscles in a freely moving primate. The algorithm performed well in both cases: it provided reliable estimates of the system output and significantly reduced the number of inputs needed for output prediction. For example, although physiological recordings from up to 40 different neuronal signals were available, the input selection algorithm reduced this to 10 neuronal signals that made significant contributions to the recorded EMGs.