Reconfigurable architectures provide the user the capability to couple performance typical of hardware design with the flexibility of the software. This paper presents the design of AES/Rijndael on a dynamically reconfigurable architecture. A performance improvement of three order of magnitude was shown compared to the reference code and up to 24times speed-up figure wrt fast C implementations over a RISC processor. A maximum throughput of 546 Mbit/sec is achieved. Compared to prior art, a better energy efficiency with respect to the other programmable solutions was shown, obtaining up to 3 Mbit/sec/mW

Embedded real-time multimedia applications pose several challenges in order to satisfy increasing quality of service (QoS) and energy consumption constraints, that are hardly matched by the capabilities of general-purpose standard processors. Reconfigurable processors, coupling the flexibility of software-programmable devices with the computational efficiency of application specific architectures, represent an appealing trade-off for next generation devices in the digital signal processing application domain. In this paper, we present a benchmarking application for the XiRisc reconfigurable processor, based on a public release of the MPEG-2 video encoder. The introduction of the reconfigurable logic gives a 5/spl times/ performance improvement and a 66% energy saving.

In this paper we present the new version of a multi-context reconfigurable datapath called PiCoGA (pipelined configurable gate array). The device provides a clear interface model and can be easily embedded in SoC systems where low power consumption and high computation capability are required. New logic cells and routing architecture have been designed for an efficient implementation of computation-intensive algorithms. The integration of a dedicated control unit for pipeline activity control provides a dataflow computational model which is easy to be integrated in a SoC. The embedded datapath has been designed using a 0.13 /spl mu/m CMOS technology. The implementation of several functions in the datapath achieves an average gate density of 1.3 KGates/mm/sup 2/ for each of the four available contexts.

In the field of embedded systems, reconfigurable processors, composed of a standard processor core coupled with a reconfigurable device, are gaining more and more importance. Algorithm developers are facing the issue of mapping applications on configurable hardware, without a specific knowledge of the underlying architecture. In this paper, we present a modular data flow control unit for a reconfigurable datapath, which can be easily programmed starting from the C description of the required functionality.

Multi-context FPGAs are a convenient solution for run-time reconfiguration, but they suffer from large area occupation. This is mainly due to programmable interconnect configuration memories which need to be replicated as many times as the number of contexts. This limitation can be overcome with a DBM (Decoder Based Multicontext) routing architecture which introduces a decoding stage between configuration memories and routing structures, so that the number of SRAM cells can be highly reduced. Both the switch and connect blocks have been designed, at the architectural and schematic level. A suitable router for DBM structures has also been developed. The results show that the approach adopted requires on average only 5% more tracks whereas the device area occupation is reduced up to 40%. We also show that DBM routing architecture does not affect the critical path delay, due to the reduction of the routing wire length.

In recent years the challenge of high performance, low power retargettable embedded system has been faced with different technological and architectural solutions. In this paper we present a new configurable unit explicitly designed to implement additional reconfigurable pipelined datapaths, suitable for the design of reconfigurable processors. A VLIW reconfigurable processor has been implemented on silicon in a standard 0.18 μ m CMOS technology to prove the effectiveness of the proposed unit. Testing on a signal processing algorithms benchmark showed speedups from 4.3x to 13.5x and energy consumption reduction up to 92%.

The complexity of the algorithms used in speaker verification is often not suitable for low power applications or HW platforms having small portions of memory available (smartcard). This paper presents a text-prompted recognition system composed of two blocks performing speaker verification and text confirmation. In both cases we made an effort to use low complexity HMM models of voiceprint and phonemes to be able to adopt strong simplification in probability computation. As far as the normalization process is usually the computationally most intensive process, we propose new efficient normalization techniques for both speaker verification and text confirmation. Low complexity is also achieved adopting smart quantization of features and model parameters. In spite of simplicity we report an Equal Error Rate (EER) of 1.2% for speaker verification and of 0.7% for text confirmation using 3 second speech utterances. Memory requirements are also kept small: less than 450 bytes are needed for speaker voiceprints.