We propose a real-world data exchange framework based on the concept of data ownership. The most important issues with these data are the protection of user privacy and preserve the value of the information derived from the data to consumers. This framework enables the protection of privacy and enables maximum leverage of real-world data belonging to each person at the same time. In our framework, real-world data and its information value are managed and protected by the personal agent system that works on each person's authority. On that basis, the information value can be exchanged and leveraged using a market mechanism that distributes transactions of queries and answers concerning the data. We also present the basic design of the framework and its personal agent system that works on multiple user devices.

To make communication a comfortable experience for users, we have developed a middleware called communication service concierge (CSC). This is a network middleware for distributed environments, and it consists of communication resource management (CRM) and communication logic management (CLM). Communication service concierge realizes comfortable communications by combining CRM and CLM. Communication logic management provides a framework to directly operate communication data. Communication resource management provides a framework on which downloadable software components can be executed on distributed platforms, and plays a primary role in controlling CSC's communication. Using Java, we implemented CRM on OSGi service platforms, which provide dynamic executions of the software components locally. In other words, CRM provides a distributed agent computing feature for OSGi. In this paper we describe the roles and implementations of CRM1 especially for security functions, as well as describing how CRM's software components work cooperatively.

In today's Internet, which includes diverse and complex network technologies and services, it is difficult to achieve 'comfortable communication' that satisfies network users from the viewpoint of aspects such as communication usability, availability, quality and safety. To alleviate these problems and make communication a comfortable experience for users, we have developed a middleware named communication service concierge (CSC). CSC focuses on communication dataflow and coordinates various resources affecting the behavior of the flow, such as network applications, protocols, network devices and computing equipment. These elements can be scattered throughout the end-to-end communication link of the dataflow. CSC provides a distributed communication control framework, which improves user satisfaction on the basis of agent computing using configurable and downloadable software components. The paper briefly describes the design concept and basic architecture of CSC, as well as two prototype applications for it that are associated with home networking and mobile computing. These are the most effective ways in which CSC helps users to achieve more comfortable communication.

This paper describes a project dedicated to developing an improved (in terms of usability) version of our previous telecommunication-oriented field programmable gate array (FPGA), and its applications. To achieve this goal, we adopt several challenging design strategies. First, we determine the new FPGA architecture based on a quantitative evaluation carried out to optimize the interaction between the FPGA and CAD algorithms. In addition, we create a new chip design environment that allows semi-automatic test pattern generation and cross-checking between logic and layout design. Furthermore, a dedicated CAD system is developed based on a consideration of the evaluation results and the characteristics of the FPGA. As a result of these design strategies, the FPGA and CAD system are well-balanced, and even though the FPGA has very rich routing resources, the routing process can be finished quickly without sacrificing application-circuit performance. The FPGA is applied to several reconfigurable systems for telecommunications, and is found to offer the required functions and good performance.

We have developed an architecture-oriented routing method for a telecommunications FPGA (Field-Programmable Gate Array) which has rich hierarchical routing resources. Our routing method consists of four routing procedures, each of which are related to a specific part of the routing resource architecture of the FPGA. It can accomplish routing results almost five times faster than a reference method that does not consider the routing resource architecture. The key idea in our approach is to reduce the number of possible resource candidates by referring to both the logical net structure and the FPGA resource architecture. We apply different routing algorithms according to the amount and architecture of candidate routing resources. Experiments show that our architecture-oriented method is more effective than conventional single-algorithm-based methods.

In designing FPGAs, it is important to achiev e a good balance bet w een the number of logic blocks, suc h has Look-Up Tables (LUTs), and wiring resources. It is difficult to find an optimal solution. In this paper, w e presen t an FPGA design methodology to efficiently find well-balanced FPGA architectures. The method covers all aspects of FPGA development from the architecture-decision process to physical implementation. It has been used to develop a new FPGA that can implement circuits that are twice as large as those implementable with the previous version but with half the number of logic blocks. This indicates that the methodology is effectiv e in dev eloping well-balanced FPGAs.

This paper presents a novel system architecture that combines tightly coupled field programmable gate arrays (FPGA's) and a microprocessing unit (MPU) that we have developed. This system architecture comprises three main programmable devices which yield high flexibility. These devices are a reduced instruction set computer (RISC)-type MPU with memories, programmable interconnection devices, and FPGA's. This system supports various styles of coupling between the FPGA's and the MPU which makes several data processing operations more effective. Furthermore, we indicate the most suitable applications for the system. They are telecommunication data processes involving complex protocol operations and network control algorithms. In this paper, two applications of the system are given. One is for operation, administration, and management (OAM) cell processing on an asynchronous transfer mode (ATM) network. The other is a dynamic remote reconfiguration protocol that enables the functions of the transport data processing system to be updated or changed on-line.

This paper presents a novel system architecture applicable to high-performance and flexible transport data processing which includes complex protocol operation and a nehvork control algorithm. We developed a new tightly coupled Held Programmable Gate Array (FPGA) and Micro-Processing Unit (MPU) system named. Yet Another Re-Definable System (YARDS). It comprises three programmable devices which equateto high flexibility. These devices are the RISC-type MPU with memories, programmable inter-connection devices, and FPGAs. Using these, this system supports various styles of coupling between the FPGAs and the MPU which are suitable for constructing transport data processing. In this paper, two applications of the systemin the telecommunications field are given. One is an Operation, Administration, and Management (OAM) cell operations on an AsynchronousTransfer Mode (ATM) network. The other is a dynamic configuration protocol enables the updateor changeof the functions of the transport data processing system on-line. This is the first approach applying the FPGA/MPU hybrid system to the telecommunications field.

This paper proposes a new processor architecture for manipulating protocols in digital signal transport systems. To realize flexible and high-performance digital signal transport systems, the architecture has unique application-specific hardware with a core CPU. It is derived from an analysis of functions in real systems. A computer simulation confirms the efficiency of the architecture.

A new FPGA (Field Programmable Gate Array) is developed for high-speed digital telecommunication systems. As architecture is based on the fundamental characteristics extracted from an analysis of actual systems. The FPGA has several unique features for realizing high-speed transport data processing. It allows us to build the high-performance components that are frequently used in transport data processing. In addition, its inter-chip connection mechanism enables us to build flexible multi-FPGA modules. Furthermore, we introduce a dedicated CAD system for the FPGA. We design several actual transport processing circuits on the FPGA using the CAD system and evaluate them. Experimental results show that the device has the potential to realize practical systems.

This paper presents a new technique for improving the performance of a synchronous circuit configured as a look-up table based FPGA without changing the initial circuit configuration; only the register location is altered. It improves clock speed and data throughput at the expense of latency. One of the most significant benefits realized by this approach is that the time-consuming and user-uncontrollable reconfiguration processes, i.e., remapping, replacement, and rerouting, are unnecessary when improving circuit performance. After applying our technique to some benchmark circuits, the average performance improvement was 33% for six combinational circuits, and 25% for 18 sequential circuits.>

This paper discusses a new architecture for programmable hardware targeted at high-speed digital telecommunication systems and describes a preliminary design. The basic architecture of the programmable hardware is proposed based on the characteristics of functions and an analysis of logic used in actual communication subsystems performing high-speed bit level operations. The proposed architecture, called PROTEUS, includes a pipeline structure of logic and latch groups, and a 2-stage logic block structure that consists of small LUTs and wide gates. The design strategy of a prototype chip and the CAD techniques used to achieve the required performance are also discussed.>