Static Random Access Memories (SRAMs) are key components of modern VLSI designs and a major bottleneck to technology scaling as they use the smallest size devices with high sensitivity to manufacturing details. Analysis performed at the "schematic" level can be deceiving as it ignores the interdependence between the implementation layout and the resulting electrical performance. We present a computational framework, referred to as "Virtual SRAM Fab", for analyzing and estimating pre-Si SRAM array manufacturing yield considering both lithographic and electrical variations. The framework is being demonstrated for SRAM design/optimization in 45nm nodes and currently being used for both 32nm and 22nm technology nodes. The application and merit of the framework are illustrated using two different SRAM cells in a 45nm PD/SOI technology, which have been designed for similar stability/performance, but exhibit different parametric yields due to layout/lithographic variations. We also demonstrate the application of Virtual SRAM Fab for prediction of layout-induced imbalance in an 8T cell, which is a popular candidate for SRAM implementation in 32-22nm technology nodes.

In this paper, we study the propagation of slew dependent bounding signals and the corresponding slew problem in static timing analysis. The selection of slew from the latest arriving signal, a commonly used strategy, may violate the rule of monotonic delay. Several methods for generating bounding signals to overcome this difficulty are described. The accuracy and monotonicity of each method is analyzed. These methods can be easily implemented in a static timer to improve the accuracy.

In this paper we compare different methods for calculating coupling noise, specially for use in the early design phase of a high performance custom design when all the detailed physical design information is not available. This analysis can be important in the design of functional blocks such as data paths in microprocessors, where if noise avoidance is included in the design planning phase, later changes in the design may be avoided. Thus, reducing the number of design iterations and overall design time. The ideal noise calculation technique should be very fast and reasonably accurate so as to account for all significant parameters that will affect the noise. We consider three different techniques and compare them with an exact analysis using a circuit simulator. It is shown that a lumped model is quite accurate for predicting noise on a variety of wire geometries up to 3 mm in length. We also propose a technique to extend this model to the practically important case when bus wires overlap only partially with neighbors.

For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the modified shortest and longest path method. The computational complexity of our algorithm is generally better than that of known algorithms in the literature. The implementation (CYCLOPSS) has been applied to an industrial chip to verify the clock schedules.

Abstract- In recent years, many new algorithms have been proposed for performing a complete timing analysis of sequential logic circuits. In this paper, we present an incremental timing analysis algorithm. When an incremental design change is made on the logic network, this algorithm will identify the portion of de-sign for which the timing is affected, and quickly derive the new arrival times and slacks. A fast incremental timing analysis is de-sirable for users doing interactive logic design. It is particularly important for a logic synthesis program, which needs to evaluate the circuit delays under many logic modifications. 1.

A hierarchical compactor, HIMALAYAS (HIerarchical MAcro LAYout ASsembler), developed for constructing big macro layouts, is discussed. The hierarchical compaction problem is formulated as an integer linear programming (ILP) problem. Two algorithms are presented to reduce the problem size, in order to make the ILP approach practical. The first algorithm reduces the number of variables to a small set of pitch variables, while the second algorithm reduces the number of equations by restricting the constraint generation within a small set of regions, called the minimum cover. These reductions bring in considerable saving in computation time for layouts with cell repetitions or cell alignments. As a result, the ILP method can be used to solve the compaction problem for very big macros. Experimental results for MCNC benchmark examples are also given.>

To develop an efficient cell compactor for practical use, the authors take the one-dimensional compaction approach, but with a mixed symbolic and shape data model. A new algorithm of automatic jog generation is employed to create jogs, not only on critical paths but also on some noncritical paths. An optimum wire length minimization algorithm is used to tighten wires and polygon edges. These algorithms help reduce both the cell size and the parasitic, and hence produce high-quality layouts. The compactor has been used at IBM in the production of several standard cell libraries and macrocells,.>

As the chip density grows, wiring circuits on a VLSI chip becomes hard. It is then important to leave feed-through channels in the layouts of cells and macros. One strategy to achieve this goal is to keep wires on their respective wiring grids. This requirement presents a new constraint to the compaction problem of cells and macros. A new efficient algorithm is proposed to solve such a compaction problem on multiple grids. The worst-case time complexity of the algorithm is O((M+1) ( mod V mod + mod E mod )). The algorithm has been implemented in a compactor and applied to the layout designs for both microprocessor chips and ASIC chips.>

A general framework for describing design rules is provided that encompasses space rules, size rules, extension rules, conditional rules, nonpositive rules, and minimum-type and maximum-type rules. Conditional rules considered include topological rules, width rules, and length rules. A fast compaction scheme was developed to handle this variety of rules in an efficient and uniform way. A compactor based on this approach was constructed that can handle several IBM technologies. In one CMOS technology, there are two width rules and two dozen topological rules, in addition to a hundred or so simple rules. The runtime performance data for several design examples, obtained on an IBM 3090 machine, are presented. It is noted that the use of conditional rules increases the computation cost only slightly, while it saves a significant amount of cell area compared with using all simple rules.>

We investigate the modeling and solution techniques of VLSI layout compaction using the constraint graph approach under various practical design considerations. In particular, we extend the graph method to the compaction of VLSI layout with mixed grid constraints in addition to the usual minimum- and maximum-type constraints. This is a mixed integer problem. We show that it can be solved by the search of effectively longest paths, and a fast algorithm is presented