This innovative practice WIP paper introduces a new method, which we call SEASIDE: SEmi-Automated Second-order Incentive-Driven Engagement to improve class attendance and participation of college students. Class attendance significantly impacts college students' academic success and personal development. To combat low participation, educators have tried various methods, however, these approaches often bring administrative challenges and need to accommodate students with disabilities. Our proposed strategy, SEASIDE, employs a mostly hands-off automated system with indirect rewards that do not alter grades in a straightforward fashion but offer benefits like assignment extensions or flexible exam options, which can potentially influence course grades. Implemented in an introductory Embedded Systems course with 240 students, this system allows students to trade participation points for assignment extensions, addressing common issues like procrastination and unexpected personal challenges. Our findings indicate that nearly 75% reported that these incentives motivated regular attendance and active participation. This approach not only enhances student engagement without directly impacting grades but also simplifies administrative processes for educators.

This full research paper uses narrative inquiry to examine the emergent `Teaching Toolbox' of a faculty member in an electrical and computer engineering department amid the backdrop of increasing class sizes. Four years ago, this ECE department received an NSF RED grant (Revolutionizing Engineering Departments) to enact large-scale curricular and culture change in the department over five years. The work under the grant has uncovered faculty-driven pedagogies that had formerly been at the periphery of the values held by the department - but did not receive much attention prior to the award. We use narrative inquiry to investigate the experiences of one electrical and computer engineering professor through a single case study. Our case study comprises multiple reflexive interviews contextualized within the history of the department through institutional documents and department meeting notes. This work is focused on the emergent pedagogical innovations one professor has enacted to [at least] maintain, [at most] improve, class engagement and participation as class sizes have increased. These pedagogical innovations reveal the multiple ways in which a professor has adapted their teaching practice to the institutional and departmental changes brought on in the past decade.

Fault attacks are a known threat to secure embedded implementations. We propose a generic technique to detect and react to fault attacks on embedded software. The countermeasure combines a micro-architecture extension in hardware with a secure trap in software. The combined extension leads to a secure exception mode to handle fault attacks. The microprocessor hardware uses a low-level hardware checkpointing mechanism to recover from fault injection. A high-level secure trap in software then enables an application-specific response. The trap is user-defined and can be co-developed with the application. The combination of hardware fault detection and recovery, with a high-level fault response policy in software leads to significantly lower overhead when compared to traditional redundancy-based techniques in hardware or software. We demonstrate a prototype implementation of the proposed secure exception mode. The prototype is based on a modified LEON3 processor and it is able to detect and respond to setup-time violation attacks. We have realized the design in a 180 nm standard cell ASIC with integrated memory. Using several driver application examples, we characterize the software and hardware overhead of the proposed solution, and we compare it to the conventional redundancy-based solutions. In our understanding this is the first proof-in-silicon processor to offer a comprehensive secure exception mode against fault-injection attacks.

Electromagnetic fault injection (EMFI) is an efficient class of physical attacks that can compromise the immunity of secure cryptographic algorithms. Despite successful EMFI attacks, the effects of electromagnetic injection (EM) on a processor are not well understood. This paper presents a bottom-up analysis of EMFI effects on a RISC microprocessor. We study these effects at three levels: at the wire-level, at the chip-network level, and at the gate-level considering parameters such as EM-injection location and timing. We conclude that EMFI induces local timing errors implying current timing attack detection and prevention techniques can be adapted to overcome EMFI.

Fault attacks on cryptographic software use faulty ciphertext to reverse engineer the secret encryption key. Although modern fault analysis algorithms are quite efficient, their practical implementation is complicated because of the uncertainty that comes with the fault injection process. First, the intended fault effect may not match the actual fault obtained after fault injection. Second, the logic target of the fault attack, the cryptographic software, is above the abstraction level of physical faults. The resulting uncertainty with respect to the fault effects in the software may degrade the efficiency of the fault attack, resulting in many more trial fault injections than the amount predicted by the theoretical fault attack. In this contribution, we highlight the important role played by the processor microarchitecture in the development of a fault attack. We introduce the microprocessor fault sensitivity model to systematically capture the fault response of a microprocessor pipeline. We also propose Microarchitecture-Aware Fault Injection Attack (MAFIA). MAFIA uses the fault sensitivity model to guide the fault injection and to predict the fault response. We describe two applications for MAFIA. First, we demonstrate a biased fault attack on an unprotected Advanced Encryption Standard (AES) software program executing on a seven-stage pipelined Reduced Instruction Set Computer (RISC) processor. The use of the microprocessor fault sensitivity model to guide the attack leads to an order of magnitude fewer fault injections compared to a traditional, blind fault injection method. Second, MAFIA can be used to break known software countermeasures against fault injection. We demonstrate this by systematically breaking a collection of state-of-the-art software fault countermeasures. These two examples lead to the key conclusion of this work, namely that software fault attacks become much more harmful and effective when an appropriate microprocessor fault sensitivity model is used. This, in turn, highlights the need for better fault countermeasures for software.

We propose a system-level solution in designing process variation aware (PVA) scalable-throughput many-core systems for energy constrained applications. In our proposed methodology, we leverage the benefits of voltage scaling for obtaining energy efficiency while compensating for the loss in throughput by exploiting parallelism present in various DSP designs. We demonstrate that such a hybrid method consumes 6.27%- 28.15% less power as compared to simple dynamic voltage scaling over different workload environments. Design details of a prototype chip fabricated on 90 nm technology node and its findings are presented. Chip consists of 8 homogeneous FIR cores, which are capable of running from near-threshold to nominal voltages. In our 20 chip population, we observe 7% variation in speed among the cores at nominal voltage (0.9V) and 26% at near threshold voltage (0.55V). We also observe 54% variation in power consumption of the cores. For any desired throughput, the optimum number of cores and their optimum operating voltage is chosen based on the speed and power characteristics of the cores present inside the chip. We will also present analysis on energy-efficiency of such systems based on changes in ambient temperature.

Previously used ICs, which are resold as new, result in undue lost revenue, cause lower performance, reduced life span, and even catastrophic failure of platforms and systems. Non-invasive and inexpensive techniques are needed to establish the authenticity of such ICs that do not have special in-built structures for counterfeit detection. Although delay of circuit increases with its age, it cannot directly reveal the age of the chip, as it is also greatly influenced by process variation. In this work, we show that the relationship between two or more paths within the chip is a great indicator of its age. Using the proposed statistical and circuit-level technique, we observe over 97% correct detection of an aged IC from a new IC.

The main aim of NIST's SHA-3 competition is to choose the new secure hash standard which will become successor of SHA-2. Analysing the strength of candidates in terms of hardware performance is complicated due to presence of different platforms such as FPGA, ASIC. Within them, implementation in an ASIC platform can be challenging due to different choices available during implementation. In this study, we will present these choices and also present an approach to evaluate the impact of these choices on the performance characteristics of SHA-3 finalists. This article will help NIST as well as cryptographers in better understanding the ASIC benchmarking results presented by different research groups.

In order to combat the exponentially growing leakage current in modern microprocessors, researchers have recently focused on very fine-grained functional unit power gating in which units of a microprocessor, including components of the ALU and floating point processor, are quickly shut off when not in use. This method is especially effective for Ultra-Low-Voltage (ULV) processors, where the slower clock periods makes leakage especially severe. In this paper, we investigate many of the important aspects of highly aggressive functional unit power gating in the context of ULV operation. Using an optimization framework, we demonstrate that functional unit power gating with an Ideal Policy results in an average of a 39.3% drop in total functional unit energy across a range of benchmarks. Next, we examine two very simple hardware-based power gating policies that achieve near-ideal results with very little overhead. Finally, we compare a newer style of ultra-low-voltage logic, Sense-Amplifier Pass Transistor Logic (SAPTL), to CMOS and show that it requires footers that are an eighth of the size and consumes about 100 times less energy on boot-up. With this lower overhead, total energy is reduced by 49.6%.

Throughout the NIST SHA-3 competition, in relative order of importance, NIST considered the security, cost, and algorithm and implementation characteristics of a candidate [1]. Within the limited one-year security evaluation period for the five SHA-3 finalists, the cost and performance evaluation may put more weight in the selection of winner. This work contributes to the SHA-3 hardware evaluation by providing timely cost and performance results on the first SHA-3 ASIC in 0.13 μm IBM process using standard cell CMOS technology with measurements of all the five finalists using the latest Round 3 tweaks. This article describes the SHA-3 ASIC design from VLSI architecture implementation to the silicon realization.

A rapidly growing class of battery constrained electronic applications are those with very long sleep periods, such as structural health monitoring systems, biomedical implants, and wireless border security cameras. The traditional method for sleep-mode power reduction, transistor power gating, has drawbacks, including performance loss and residual leakage. This article presents a thorough evaluation of a new nanotechnology-enabled power gating structure, CMOS-compatible NEMS switches, in the presence of aggressive supply voltage scaling. Due to the infinite off-resistance of the NEMS switches, the average power consumption of an FFT processor performing 1 FFT per hour drops by around 30 times compared to a transistor-based power gating implementation. Additionally, the low on-resistance and nanoscale size means even with current prototypes, area overhead is as much as 5 times lower, with much room for improvement. The major drawback of NEMS switches is the high activation voltage, which can be many times higher than typical CMOS supply voltages. We demonstrate that with a charge pump, these voltages can be generated on-die, and the energy and bootup delay overhead is negligible compared to the FFT processing itself. These results show that NEMS-based power-gating warrants further investigation and the fabrication of a prototype.

Voltage scaling has been a prevalent method of saving energy for energy-constrained applications. However, current technology trends which shrink transistors sizes exacerbate process variation effects in voltage-scaled systems. Large variations in transistor parameters result in high variation in performance and power across the chip. These effects, if ignored at the design, stage, will result in unpredictable behavior when deployed in the field. In this article, we leverage the benefits of voltage scaling methodology for obtaining energy efficiency and compensate for the loss in throughput by exploiting parallelism present in the various DSP designs. We show that such a hybrid method consumes 8%--77% less power, compared to simple dynamic voltage scaling over different throughputs. We study this system architecture in two different workload environments: static and dynamic. We show that to achieve the highest level of energy efficiency, the number of cores and the operating voltages vary widely between a BASE design versus a process variation-aware (PVA) design. We further demonstrate that the PVA design enjoys an average of 26.9% and 51.1% reduction in energy consumption for the static and dynamic designs, respectively. Since different cores will have a wide range of speeds at operating voltages close to near/sub-thresholds due to process variation, we gather characteristic behavior of each core. With knowledge of the core speeds, we can further increase the energy efficiency. Furthermore, in this article, we show that of this methodology will be 49.3% more energy efficient, compared to that building the system with no knowledge about the characteristics of each core.

This paper presents a case for using Nano-Electro-Mechanical-System switches for power gating idle functional units of an embedded microprocessor. We achieve an average of 26% total energy savings, with a worst-case 5% increase in cycles. Our work includes detailed comparison with transistor switches, actuation circuitry design, identification of desired switch parameters, and device lifetime analysis.

The NIST SHA-3 competition aims to select a new secure hash standard. Hardware implementation quality is an important factor in evaluating the SHA-3 finalists. However, a comprehensive methodology to benchmark five final round SHA-3 candidates in ASIC is challenging. Many factors need to be considered, including application scenarios, target technologies and optimization goals. This work describes detailed steps in the silicon implementation of a SHA-3 ASIC. The plan of ASIC prototyping with all the SHA-3 finalists, as an integral part of our SHA-3 ASIC evaluation project, is motivated by our previously proposed methodology, which defines a consistent and systematic approach to move a SHA-3 hardware benchmark process from FPGA prototyping to ASIC implementation. We have designed the remaining five SHA-3 candidates in 0.13 μm IBM process using standard-cell CMOS technology. In this paper, we discuss our proposed methodology for SHA-3 ASIC evaluation and report the latest results based on post-layout simulation of the five SHA-3 finalists with Round 3 tweaks.

In this paper we study the effectiveness of two power gating methods - transistor switches and MEMS switches - in reducing the power consumption of a design with a certain target throughput. Transistor switches are simple, but have fundamental limitations in their effectiveness. MEMS switches, with zero leakage in the off state, have achieved much focus over the past decade in the RF field, but have only very recently been explored in the context of power gating. In this paper we study both methods in conjunction with voltage scaling and show that MEMS switches are the superior choice over a wide range of target throughputs, especially low-throughput applications such as wireless sensor networks and biomedical implants. We also show that the architectural choices and operating conditions in a throughput-aware design can be profoundly different when using MEMS switches as opposed to transistor switches. For instance, while transistor switches favor smaller and slower architectures, the MEMS switches favor larger and faster designs when the target throughput is low. Moreover, while the optimal operating voltage of a transistor-switched design resides in the subthreshold region, that of a MEMS-switched design can be above or near the threshold voltage. To prove this, we provide both a mathematical analysis and experimental results from four different FFT architectures.

Subthreshold voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. This is beneficial in embedded applications that must run off of batteries and scavenged energy. Subthreshold operation has been proven to be very effective by several successful prototypes in the recent years, yet there is no fast and effective way for designers to estimate power and delay of a design operating in the subthreshold region. Traditional gate-level simulation tools are not set up to perform timing and power analysis in the subthreshold region and transistor level simulations are very time consuming due to the accuracy required to measure the very low levels of current. This paper presents a simulation framework that can accurately characterize a circuit from nominal voltage, all the way down into the subthreshold region. This framework uses the nominal frequency and power of a target circuit and a normalized ring oscillator curve to characterize the circuit at lower voltages. The contribution of this paper is a detailed analysis of this framework in the presence of a variety of design parameters such as bus lengths, transistor widths, etc. The simulation framework is extremely quick and accurate across a wide variety of circuits.

Subthreshold circuits have drawn a strong interest in recent ultralow power research. In this paper, we present a highly efficient subthreshold microprocessor targeting sensor application. It is optimized across different design stages including ISA definition, microarchitecture evaluation and circuit and implementation optimization. Our investigation concludes that microarchitectural decisions in the subthreshold regime differ significantly from that in conventional superthreshold mode. We propose a new general-purpose sensor processor architecture, which we call the Subliminal Processor. On the circuit side, subthreshold operation is known to exhibit an optimal energy point (Knin)- However, propagation delay also becomes more sensitive to process variation and can reduce the energy scaling gain. We conduct thorough analysis on how supply voltage and operating frequency impact energy efficiency in a statistical context. With careful library cell selection and robust static RAM design, the Subliminal Processor operates correctly down to 200 mV in a 0.13-mum technology, which is sufficiently low to operate at Vmin. Silicon measurements of the Subliminal Processor show a maximum energy efficiency of 2.6 pJ/instruction at 360 mV supply voltage and 833 kHz operating frequency. Finally, we examine the variation in frequency and Vminacross die to verify our analysis of adaptive tuning of the clock frequency and Vminfor optimal energy efficiency.

The Discrete Wavelet Transform (DWT) is a means to analyze the frequency content of a signal and has extensive uses, including the JPEG2000 codec. Many portable and battery operated applications of DWT are expected in the near future that require a low power implementation of this transform. In this paper, a parallel VLSI implementation of a 2D lifting-based DWT processor is presented that is scalable from 2 to 256 parallel units. This design benefits from an efficient data distribution module to the parallel units, which constitutes a small overhead, and is able to significantly benefit from voltage scaling to achieve energy efficiency. In our design, the number of parallel units is increased and their speed is reduced through voltage scaling, while maintaining a constant throughput. Our results show that the optimal operating voltage of the parallel units, for a target throughput of 200MHz,4 is 386mV. This is below the threshold voltage, which is the voltage that turns the transistors on. Since operating a circuit in subthreshold voltage consumes 100+ times less power than running it at nominal voltage, our design is able to provide the same throughput as a reference pipelined implementation with 26 times less power consumption.

Side-channel attacks on the power consumption of a circuit correlate the variations of the power consumption with the internal data processing of that circuit, and can reveal internal secrets. For example, cryptographic circuits can be power-analyzed to reveal their secret keys. The use of the subthreshold-voltage circuits to implement those circuits makes their side-channel power analysis significantly more difficult. The reduced operating voltage, as well as the proportionally larger leakage, result in power variations that are orders of magnitude less than the super-threshold case, and hence much more difficult to measure. This paper will present an analysis of subthreshold voltage technology for secure circuit design, and propose potential applications.

Memory is one of the most significant detrimental factors in increasing the cost and area of embedded systems, especially assemiconductor technology scales down. Code compression techniques have been employed to reduce the memory requirement of the system without sacrificing its functionality. Bitmask-based code compression has been demonstrated to be a successful technique that produces low compression ratios while having a fast and simple decompression engine. However, the current approach requires dictionary sizes of +16K bytes to produce acceptable results, adding significant overhead to the system. In this paper, we develop a new hybrid encoding method that combines the traditional bitmask-based encoding and prefix-based Huffman encoding as well as a new dictionary selection technique based on a non-greedy algorithm. The combination of these two new methods reduces the compression ratio by 9-20% and performs well with small dictionary sizes.

In this paper we present a second-generation sensor network processor which consumes less than one picoJoule per instruction (typical processors use 100's to 1000's of picoJoules per instruction). As in our first-generation design effort, we strive to build microarchitectures that minimize area to reduce leakage, maximize transistor utility to reduce the energy-optimal voltage, and optimize CPI for efficient processing. The new design builds on our previous work to develop a low-power subthreshold-voltage sensor processor, this time improving the design by focusing on ISA, memory system design, and microarchitectural optimizations that reduce overall design size and improve energy-per-instruction. The new design employs 8-bit datapaths and an ultra-compact 12-bit wide RISC instruction set architecture, which enables high code density via micro-operations and flexible operand modes. The design also features a unique memory architecture with prefetch buffer and predecoded address bits, which permits both faster access to the memory and smaller instructions due to few address bits. To achieve efficient processing, the design incorporates branch speculation and out-of-order execution, but in a simplified form for reduced area and leakage-energy overheads. Using SPICE-level timing and power simulation, we find that these optimizations produce a number of Pareto-optimal designs with varied performance-energy tradeoffs. Our most efficient design is capable of running at 142 kHz (0.1 MIPS) while consuming only 600 fJ/instruction, allowing the processor to run continuously for 41 years on the energy stored in a miniature 1g lithium-ion battery. Work is ongoing to incorporate this design into an intra-ocular pressure sensor.

Sensor network processors and their applications are a growing area of focus in computer system research and design. Inherent to this design space is a reduced processing performance requirement and extremely high energy constraints, such that sensor network processors must execute low-performance tasks for long durations on small energy supplies. In this paper, we demonstrate that subthreshold-voltage circuit design (400 mV and below) lends itself well to the performance and energy demands of sensor network processors. Moreover, we show that the landscape for microarchitectural energy optimization dramatically changes in the subthreshold domain. The dominance of leakage power in the subthreshold regime demands architectures that i) reduce overall area; ii) increase the utility of transistors; while iii) maintaining acceptable CPI efficiency. We confirm these observations by performing SPICE-level analysis of 21 sensor network processors and memory architectures. Our best sensor platform, implemented in 130nm CMOS and operating at 235 mV, only consumes 1.38 pJ/instruction, nearly an order of magnitude less energy than previously published sensor network processor results. This design, accompanied by bulk-silicon solar cells for energy scavenging, has been manufactured by IBM and is currently being tested.