This article presents a 24-MHz fast startup crystal oscillator (XO) with a phase-interpolator-assisted synchronized injection technique. The technique ensures phase consistency between the injection source and the crystal resonance, even with a 2% injection-$\Delta F$, enhancing the robustness of the startup under different PVT conditions. Additionally, we propose a differential peak detection technique to detect the phase error incurred by$\Delta F$. Such a peak detection technique shortens the auxiliary non-injection period during startup to merely four cycles, thereby maximizing the injection percentage to 97.4% and enhancing the startup’s efficacy. Fabricated in the 40-nm CMOS process, the XO achieves a 6.9-$\mu $s startup time (166 cycles) with a startup energy of 4.8 nJ under a 1-V$V_{\text {DD}}$. Furthermore, the startup time varies by ±4.4%, ±3.6%, and ±5.1% (worst case) over$\Delta F$(0.25% to 2%), temperature (−40 to$85~^{\circ }$C), and$V_{DD}$(0.95 to 1.05 V) variations, respectively. The XO’s phase noise in the steady-state is −137.8dBc/Hz at the 1-kHz offset, with a power consumption of$63~\mu $W.

This paper presents an analysis of differential-drive cross-coupled (DDCC) rectifier in high-sensitive RF energy harvesting system. The relationship between input RF voltage and output DC voltage with gate compensation voltage is built. Meanwhile, effects of mismatches on differential input branches are discussed. To verify the mismatch analysis, simulations on both the amplitude mismatch and the phase mismatch are conducted under standard CMOS 180nm process. Both theorical analysis and simulations indicate that the amplitude mismatch features little effect on the output DC voltage but the phase mismatch plays a much more important role to decrease the output voltage of DDCC rectifiers.

As transistor feature size decreases, timing analysis under different PVTs has become a critical challenge. Statistical Static Timing Analysis (SSTA) can achieve higher accuracy than STA. However, SSTA needs to make a lot of repetitive calculations, which is time-consuming. Therefore, we propose a post-routing statistical delay prediction framework, Global Graph Neural Network (Global-GNN). In order to overcome the problem of insufficient information in the cell embedding generated by the limitation of receptive field in traditional GNN, which leads to the poor performance of the prediction model. We optimize the updating cell embedding method so that the cell embedding contains not only local information but also global information. The cell embedding and PVT information is used to predict the path mean delay mean and path squared deviation for the current operating condition, and thus to calculate the post-routing path statistical delay. Experiments are done based on the ISCAS’89, OpenCores, and ITC’99 benchmarks of the TSMC 28nm technology. Under different PVTs the value of$R^{2}$ranges from 0.849 to 0.999, and the speed is at least$215 \times $higher than the traditional post-routing path statistical delay calculation method. At the same time, compared with the competing model, the$R^{2}$of Global-GNN can reach 0.999, and the minimum running speed can reach 0.282 s, which is obviously better than the competing model.

During the DFT planning period, one of the design challenges is how to determine the core parameters of the DFT, so as to ensure the low cost, high efficiency and high reliability of the DFT. An optimized DFT technology based on machine learning is proposed in this paper. The method mainly includes four steps: data collection, optimal prediction model selection, parameter prediction, and optimal configuration calculation. This method can predict the results of all configurations in the selectable range with a small cost, thereby calculating the optimal DFT structure. The results of experiment show that the method can effectively calculate the optimal configuration of the design. For the most important test coverage parameter in DFT, the average prediction error is only 0.2767%.

In this paper, an adaptive scan chain structure based plaintext analysis technique is proposed. The technology is implemented by three circuits, including adaptive scan chain circuit, plaintext analysis circuit and controller circuit. The plaintext is analyzed whether meet the characteristics of the differential cryptanalysis in the plaintext analysis module. The adaptive scan chain contains MUX, XOR and traditional scan chain, which is easy to implement. If the last bit of two plaintexts differs by one, the adaptive scan chain is controlled to input them into different scan chain. Compared with complicated scan chain, the structure of adaptive scan chain is variable and can mislead attackers who use differential cryptanalysis attack. Through experimental analysis, it is proved that the security of the adaptive scan chain structure is greatly improved.

Based on the principle of equivalent sampling, a low-cost ultra-wideband ground penetrating radar (GPR) receiving circuit is proposed in this paper. The circuit is mainly composed of three parts: high-precision delay control circuit, sampling pulse generating circuit and equivalent sampling circuit. The Step-Recovary Diode(SRD) and the avalanche transistor are used to generate the sampling pulse signal, and the step recovery diode is used as the front sharpening circuit to drive the avalanche transistor. As a result, a sampling pulse signal with a bottom pulse width of about 430 ps and an amplitude of up to 1.5 V is generated. RF transistors are used in the equivalent sampling circuit to obtain a new triode equivalent sampling circuit which replaces a complex diode bridge circuit with a triode. The equivalent sampling circuit is verified by using a 2ns, 500mV triangular wave as the sampled signal. After being sampled and held, the signal is stepped, and each sampling point corresponds to the signal to be taken, and the holding time is 100 ns. In the time domain, the ultrawideband pulse waveform is stretched by a factor of 1000, and the relative sampling frequency is reduced by a factor of 1000. Meanwhile, at the same time, the original pulse width of 2ns becomes a 2us waveform. Through the equivalent sampling method, the receiving circuit can post-process the sampled signal by using an ADC with a low sampling frequency and a low price. The equivalent sampling method solves the problem of dependence on ultra-high-speed A/D chips and greatly reduces the hardware cost of system design.

A novel Built-In Self-Test (BIST) algorithm is proposed in this paper, which is used for testing low-voltage SRAM. The algorithm is the improvement of March C+ algorithm, which integrates the continuous write 0 and write 1 operations to cover more fault models like Read Destructive Coupling Fault (CFrd), Write Destructive Coupling Fault (CFwd) and Write Disturb Fault. Consequently, higher fault coverage is achieved than traditional March algorithm. The proposed algorithm is implemented by user defined algorithm (UDA) of Mentor tools. In order to verify the effectiveness of the algorithm, a low-voltage 8T SRAM chip is designed and tested based on SMIC 40nm LL CMOS process. Simulation results show that the proposed BIST algorithm named March-LV for low-voltage SRAM arrays covers 100% target faults. The test results further verify the feasibility of the algorithm.