In this paper we propose a new methodology, called parametric on chip variation (POCV) analysis, to determine local process variation effects on the timing of designs. The proposed methodology requires relative delay and parasitic variations of cells and interconnects, respectively. Once this information is provided, delays and arrival times are propagated to calculate slacks as a function of these relative variations. A key characteristic of the POCV analysis is that it does not require a statistical library characterization or statistical RC extraction. The POCV method has been implemented in a timing analysis software, and tested on multiple production designs on 65nm and 45nm technology nodes, including multi-million instance designs. Our observation was that compared to the existing methods, POCV removes unrealistical pessimism on the setup paths and captures risks on the hold paths, with no changes to the existing timing sign-off environment.

The large-scale process and environmental variations for today's nanoscale ICs require statistical approaches for timing analysis and optimization. In this paper, we demonstrate why the traditional concept of slack and critical path becomes ineffective under large-scale variations and propose a novel sensitivity framework to assess the ldquocriticalityrdquo of every path, arc, and node in a statistical timing graph. We theoretically prove that the path sensitivity is exactly equal to the probability that a path is critical and that the arc (or node) sensitivity is exactly equal to the probability that an arc (or a node) sits on the critical path. An efficient algorithm with incremental analysis capability is developed for fast sensitivity computation that has linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industrial examples.

The large-scale process and environmental variations for today's nanoscale ICs are requiring statistical approaches for timing analysis and optimization. Significant research has been recently focused on developing new statistical timing analysis algorithms, but often without consideration for how one should interpret the statistical timing results for optimization. In this paper (Li et al., 2005) we demonstrate why the traditional concepts of slack and critical path become ineffective under large-scale variations, and we propose a novel sensitivity-based metric to assess the "criticality" of each path and/or arc in the statistical timing graph. We define the statistical sensitivities for both paths and arcs, and theoretically prove that our path sensitivity is equivalent to the probability that a path is critical, and our arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability is described for fast sensitivity computation that has a linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples.

This paper proposes an analytical inductance extraction model for characterizing min/max values of typical on-chip global intercon-nect structures, and a corresponding delay metric that can be used to provide RLC delay prediction from physical geometries. The model extraction and analysis is efficient enough to be used within optimization and physical design exploration loops. The analytical min/max inductance approximations also provide insight into the effects caused by inductances.

The Elmore delay is the metric of choice for performance-driven design applications due to its simple, explicit form and ease with which sensitivity information can be calculated. However, for deep submicron technologies, the accuracy of the Elmore delay is insufficient. In this paper we formulate a delay model using a provably stable two pole waveform response that provides a unique mapping between four moments and a specific delay value. Unlike traditional moment matching, this two-pole model permits us to precharacterize the delays, and store them in a table, as a mapped function of three parameters. The model also provides an explicit expression for the peak noise induced on a coupled line as a function of the same three moments. The results indicate runtimes comparable to an Elmore delay calculation but with the accuracy of an AWE approximation.

Krylov space methods initiated a new era for RLC circuit model order reduction. Although theoretically well-founded, these algorithms can fail to produce useful results for some types of circuits. In particular controlling accuracy and ensuring passivity are required to fully utilize these algorithms in practice. In this paper we propose a methodology for passive reduction of RLC circuits based on extensions of PRIMA, that is both broad and practical. This work is made possible by uncovering the algebraic connections between this passive model order reduction algorithm and other Krylov space methods. In addition, a convergence criteria based on an error measure for PRIMA is presented as a first step towards intelligent order selection schemes. With these extensions and error criterion examples demonstrate that accurate approximations are possible well into the RF frequency range even with expansions about s=0.

As IC clock frequencies approach the GHz range, the distribution of the clock signals becomes more critical in terms of controlling both skew and signal attenuation. Moreover, inductance effects are evident since RC transmission lines will overly attenuate these high-frequency clock signals. To facilitate accurate optimization of clock tree performance and skew requires simple metrics which capture these high-frequency effects. In this paper, we derive simple metrics and bounds for the phase delay and the attenuation of a periodic [RC(L)] tree response as a function of the fundamental frequency of the clock signal. These metrics are based on the first two moments of the impulse response, and are shown to further provide a mechanism for control of underdamped responses (reflections). An important result of this work is the clear demonstration that once the attenuation of the clock signal is controlled, the phase delay can be accurately captured in terms of the first-moment. Furthermore, the form of these metrics and their relationship to one another provides an excellent foundation for various forms of clock tree optimization.

This paper describes an algorithm for generating provably passive reduced-order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to macromodel stability, macromodel passivity is needed to guarantee the overall circuit stability once the active and passive driver/load models are connected. The approach proposed here, PRIMA, is a general method for obtaining passive reduced-order macromodels for linear RLC systems. In this paper, PRIMA is demonstrated in terms of a simple implementation which extends the block Arnoldi technique to include guaranteed passivity while providing superior accuracy. While the same passivity extension is not possible for MPVL, comparable accuracy in the frequency domain for all examples is observed.

Extracting the inductance of complex interconnect topologiesis a formidable task, and simulating the resulting dense partialinductance matrix is even more difficult. Furthermore, it is wellknown that simply discarding smallest terms to sparsify the inductancematrix can render the partial inductance matrix indefiniteand result in an unstable circuit model. In this paper, wedescribe a methodology for incrementally generating a sparsepartial inductance matrix based on using moments about s=0 todetermine when a sufficient number of mutual inductances havebeen captured. The minimally required mutual inductances areextracted for a provably stable model.

This paper describes PRIMA, an algorithm for generating provably passive reduced order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to requiring macromodel stability, macromodel passivity is needed to guarantee the overall circuit stability once the active and passive driver/load models are connected. PRIMA extends the block Arnoldi technique to include guaranteed passivity. Moreover, it is empirically observed that the accuracy is superior to existing block Arnoldi methods. While the same passivity extension is not possible for MPVL, we observed comparable accuracy in the frequency domain for all examples considered. Additionally a path tracing algorithm is used to calculate the reduced order macromodel with the utmost efficiency for generalized RLC interconnects.

A mathematical model for lossy, multiconductor transmission lines is introduced to facilitate the efficient application of Krylov subspace order-reduction techniques to the analysis of linear networks with transmission line systems. The model is based on the use of Chebyshev polynomial expansions for the approximation of the spatial variation of the transmission-line voltages and currents. The exponential convergence of Chebyshev expansions, combined with a simple collocation procedure, leads to a low-order matrix representation of the transmission line equations with matrix coefficients that are first polynomials in the Laplace variable s, and in which terminal transmission-line voltages and currents appear explicitly. Thus, the resulting low-order model is compatible with both Krylov subspace order-reduction methods (such as the Lanczos and the Arnoldi processes) and the modified nodal analysis formalism. The accuracy and efficiency of the proposed model, as well as its compatibility with Krylov subspace order reduction, are demonstrated through its application to the numerical simulation of several interconnect circuits.

Although numerous methods have been proposed for interconnect simulation, no single model exists for all kind of transmission line problems. This paper presents a new, single, general dispersive coupled uniform/nonuniform transmission line model which can be used for interconnect simulation in SPICE. The mathematical model is based on the use of Chebyshev polynomials for the representation of the spatial variation of the transmission-line voltages and currents. A simple collocation procedure is used to obtain a matrix representation of the transmission line equations with matrix coefficients that are first polynomials in s, and in which terminal transmission-line voltages and currents appear explicitly. Thus, the model is compatible with both the SPICE's numerical integration algorithm and the modified nodal analysis formalism.