This article presents the design and implementation of a fully differential Successive Approximation Register (SAR) analog-to-digital converter (ADC) in 65 nm UMC technology, specifically targeting biomedical applications where area efficiency is a critical requirement. The design prioritizes achieving clean and precise first-order Noise Shaping (NS) by integrating a switched-capacitor-based integrator with our proposed C-2C ladder DAC topology, which is instrumental in significantly reducing area consumption. Noise performance is optimized by carefully correlating the capacitances of the integrator and DAC, ensuring precision and stability. To achieve robust operation, the design incorporates a process, voltage, and temperature (PVT)-resilient methodology for all system blocks, providing consistent performance and reliability under challenging conditions and variations in fabrication. The implemented prototype achieves an area efficiency of 0.058 mm 2 , 10.37 ENOB over a 20 kHz Bandwidth, and operates at a 1 MHz sampling rate with a power consumption of 448 μ W . • This research exhibits for the first time, the NS SAR incorporating a C2C DAC. • The design specifications target biomedical applications, with good trade-offs. • The proposed design improves Integration for the NS-SAR. • The design aims for resilience to Process, Voltage, and Temperature Variations. • The experimental results in the Integrated Circuit prototype show the benefits.

This paper presents a novel quarter-rate Clock Data Recovery (CDR) topology, wherein the phase-tracking loop is implemented using eight Phase Interpolators (PIs). Each PI provides 15 discrete steps between every 45° phase increment, enabling the accurate detection of edge or data samples during plesiochronous operation. The PI is digitally controlled by a circuit topology that facilitates both coarse and fine phase adjustments, thereby enhancing linearity and minimizing Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) errors.Phase selection within the CDR is governed by a digital majority vote scheme and a four-bit digital counter. The design and layout were executed using 65nm CMOS technology, targeting a data rate of 10Gb/s and an operating frequency of 2.5GHz for the PI. This setup achieves an angular resolution of approximately 2.81° per code, with a standard delay of 3.125ps. The proposed system was validated through simultaneous post-layout simulations, incorporating the PI, CML2CMOS buffers, and CML latches. Additionally, Verilog-AMS simulations were used to model jitter generation within a pseudo-random bit sequence (PRBS) and to design the corresponding digital logic operations.

This paper presents the design of a 12-bit 1.5-bit/stage pipelined ADC for communications systems in MATLAB/Simulink. The model can be useful as a tool in the design of data converters. In addition is fully editable and capable to introduce as many non-idealities as the designer requires, reducing the design time. In this work, a new OFDM platform is proposed to evaluate the performance and effects of experimental analog-to-digital converters on the OFDM communication system.

This paper proposes a new low order time variant digital ΣΔ MASH modulator for fractional frequency synthesizers. The phase noise spectrum is improved as the spur tones from the fractional modulation are disabled. The usage of low order time variant MASH architectures reduces the number of levels that control the programable divider, reducing therefore the complexity and power requirements of the synthesizer.

A double sampled second order ΣΔ modulator with an analog look ahead (ALA) approach is presented. The proposed architecture provides an extra clock period to be used for the quantization. The feedforward path in both integrators allows the further reduction of the output voltage swing, relaxing also the slew-rate requirements of the op-amps. Moreover, the modulator enables the reduction of the number of quantization levels in the quantizer, thus the overall power consumption of the modulator would be significantly reduced. The proposed solution has been simulated at behavioral level by considering an improved model which takes into account the slew-rate and bandwidth limits.