Seamlessly unifying communication and sensing, sixth-generation (6G) networks are poised to transform into intelligent platforms with high spectral–energy efficiency and real-time environmental awareness. In the low-altitude economy, unmanned aerial vehicles (UAVs) enable air–ground integrated sensing and communication (ISAC) for applications such as logistics and inspection, yet most studies focus on single-UAV or homogeneous-agent designs. In contrast, this paper proposes a multi-UAV cooperative ISAC system that enables heterogeneous-agent collaboration between multiple UAVs and a ground base station (BS) for joint target sensing, tracking, and communication. The system is formulated as a posterior Cramér–Rao bound (PCRB) minimization problem under communication performance constraints, utilizing joint trajectory–beamforming optimization. To tackle the NP-hard nature of this problem, we design a curriculum-based heterogeneous-agent proximal policy optimization (C-HAPPO) algorithm, where curriculum learning guides progressive policy refinement and Kronecker/QR decomposition mitigates action dimensionality. Simulation results show that the proposed approach achieves more than a 30% improvement in sensing performance, faster convergence, and higher tracking accuracy than existing baselines, demonstrating its scalability and effectiveness for complex multi-UAV ISAC scenarios.

As the complexity and density of electronic components continue to increase, manual printed circuit board (PCB) routing has become an increasingly labor-intensive and costly task. However, the lack of large, publicly available datasets for training machine-learning (ML) models has hindered potential advancements in this field. To address this gap, we introduce PCBRouteNet, a comprehensive, large-scale dataset specifically designed to accelerate ML innovations in automated PCB routing. To handle the high complexity of PCB data and enhance extraction efficiency, we propose a dynamic, adjustable, quadrilateral network flow model. This model constructs a network flow graph composed of quadrilateral tiles, efficiently transforming the original design data into a network flow-based format. This format facilitates feature extraction for both global and detailed routing tasks. Additionally, we introduce and analyze various flow-encoding methods to explore the generalization and relationships between data size and network parameters, leveraging scaling laws. Our dataset features a diverse array of layouts with varying complexities, such as multilayer boards and high-density interconnects. Furthermore, we propose several practical ML tasks that utilize PCBRouteNet to demonstrate its potential in improving the efficiency and effectiveness of automated PCB routing solutions.

As the complexity and density of electronic components continue to grow, manual printed circuit board (PCB) routing has become an increasingly labor intensive and costly task. However, the lack of large publicly available datasets for training machine learning (ML) models has limited potential advancements in this area. To address this gap, we introduce PCBRouteNet, a comprehensive large-scale dataset specifically designed to accelerate ML innovations in automated PCB routing. To manage the high complexity of PCB data and improve extraction efficiency, we propose a dynamic, adjustable quadrilateral network flow model to construct a network flow graph composed of quadrilateral tiles. This method efficiently converts original design data into a network flow-based format, facilitating feature extraction for both global and detailed routing. Our dataset includes over 1,000 samples of real-world PCB designs, featuring diverse layouts with varying complexities, such as multi-layer boards and high-density interconnects. Additionally, we propose several practical ML tasks that utilize PCBRouteNet to showcase its potential in advancing the efficiency and effectiveness of automated PCB routing solutions.

A precision-scalable neural processing unit, considering the quantization-sensitive of each neural network layer, has large hardware redundancy in multiplication units and shift logics. In this paper, we explore a spatial parallel stochastic computing (SPSC) precision-scalable architecture to reduce hardware redundancy. The conventional SPSC multiplier has large accuracy loss, so we analyze the error component and propose an error compensation SC (ECSC) multiplier. To reduce the hardware cost, the bitbrick (BB) in fusion-based precision-scalable architecture is replaced by stochastic bitbrick (STOBB), which is composed of a fine-grained ECSC multiplier. The proposed SC architecture supports 2/4/8-bit operation. Our design is synthesized under SMIC 55nm CMOS technology. Experiments show that our design achieves a 2.048 TOPS/W energy efficiency as well as 2.21× area efficiency in comparison to the state-of-the-art designs.

As electronic devices become increasingly compact, designing printed circuit boards (PCBs) has become more challenging, particularly in the routing step, which is now more complex and time-consuming. In this work, we propose a method that applies generative pretrained transformers (GPTs) for PCB routing, referred to as GPCB routing. Initially, we convert the detailed routing information of the PCB into network flow-based encodings. Consequently, GPCB routing tokenizes routing patterns, effectively transforming the routing task into a form of token encoding prediction. To enhance prediction accuracy, we implement a 2-D sliding window with a local memory scheme, thereby expanding the sensing area of GPCB. Additionally, we propose a multi-information fusion scheme to identify the start and end points of multiple wires to further improve the prediction accuracy. Compared to existing routing methods, GPCB has the distinct advantage of learning routing strategies from human experts, breaking the limitations of traditional model-based routing approaches. Moreover, GPCB operates as a parallel routing method capable of predicting multiple routes simultaneously, resulting in significant enhancements in routing performance. Based on the experimental results, GPCB consistently outperforms in terms of routability, runtime, and wirelength.

As the size of base station antenna arrays continues to grow, even with linear processing algorithms, the computational complexity and power consumption required for massive MIMO equalization or precoding (EoP) matrix computation increase exponentially. This paper proposes an inverse matrix minibatch gradient descent (IM-MBGD) method for MIMO EoP. The proposed method leverages minibatch gradient descent to compute the pseudo-inverse of the Gram matrix instead of directly calculating the EoP matrix. Since the pseudo-inverse matrix has significantly lower dimensions compared to the EoP matrix, this approach effectively reduces computational complexity and accelerates convergence. Based on our convergence analysis, to further minimize the iteration time and improve the accuracy of the EoP matrix, we optimize the IM-MBGD method using a finite-alphabet neighborhood search. The finite-alphabet search performs neighborhood optimization to achieve the optimal solution. Compared to state-of-the-art alphabet-based equalizers, our proposed method achieves a 14-fold reduction in computational complexity for EoP matrix calculation. Furthermore, in terms of storage and the overall equalization process, our method reduces overhead by 80% compared to linear equalizers.

The complex calculations of the low-density parity-check (LDPC) decoder result in significant energy and hardware consumption. To solve the challenge, this brief describes a fully parallel stochastic LDPC decoder with a two-stage shared memory (TSM) variable node (VN). To enhance cost efficiency, our design incorporates a shared low-cost random number generator (RNG) for all 2160 channels. We introduce a TSM VN function, which demonstrates faster convergence and reduced hardware overhead in comparison with the existing methods. We have taped out the (2160, 1760) stochastic LDPC decoder in the 55-nm process. The measure results exhibit that the proposed design achieves a throughput of 57.6 Gb/s, an efficiency of 33.68 Gb/s/mm2, and a power efficiency of 4.86 pJ/bit, underlining superior performance in terms of decoding throughput, hardware efficiency, and energy conservation.

Matrix multiplication serves as the primary operation in massive multiple-input multiple-output (MIMO). However, with the continuous advancement of MIMO technology, the escalating computational complexity and the necessity for adaptable matrix multiplication in MIMO communication pose a formidable challenge. In this paper, we propose the Joint Serial-Parallel Dataflow (JSPD) mapping method for dynamic precision matrix multiplication, which relies on the utilization of Spatio-Temporal Transforms (STT) and Principal-Auxiliary Matrices (PAM). The data is initially processed serially and is mapped onto Processing Element (PE) arrays through STT transforms. Subsequently, both high-precision and low-precision components of the data are computed selectively in parallel, employing a combination of principal and auxiliary matrices. The matrix multiplication process is mapped onto the PE arrays, incorporating output-stationary and output-flow modes. Compared with the traditional fixed structure PE arrays, the JSPD mapping method improves the computational flexibility while increasing the PE cell work share ratio by 7.57% ∼ 21.86%. Meanwhile, JSPD reduces the hardware overhead by a maximum of 68% and improves hardware efficiency by 35.77%.

The growing complexity of electronic products demands more intricate Print Circuit Board (PCB) shapes. The complex-shaped PCBs often contribute to reducing efficiency in imposition process and result in material wastage. Currently, PCB imposition heavily relies on the personal experience of engineers, which is inherently uncertain and challenging to optimize. Additionally, the presence of specific PCB imposition rules leads to traditional optimization methods unsuitable for a direct solution. To address these issues, we propose an automatic PCB imposition method based on reinforcement learning. Our approach transforms the PCB imposition problem into a Markov Decision Process(MDP), decomposing the combination optimization problem into a sequential solution problem for the optimal placement of each PCB. We derive the global optimal solution by solving the optimal placement of each PCB. According to the simulation results, our approach demonstrates a 28.40% increase in utilization rate when compared to the random imposition algorithm and a 7.75% increase when compared to the greedy search algorithm.

Optimizing an appropriate design of decoupling capacitors (decaps) is a primary challenge in the field of power delivery network (PDN). A fast PDN impedance acquisition method will expedite the process and enhance the efficiency within an expansive search space for decaps optimization. In this paper, we propose a model and data fusion method to analyze the PDN impedance. The fusion method incorporates the polynomial similarity of the PDN impedance into the deep learning (DL) framework. Moreover, we reduce the dimensionality of the input to compact the network structure and decrease the training time. The experimental results demonstrate that our proposed method promotes the accuracy by 8% compared to other DL methods. In the time of generating outputs, our method is 80 times faster than conventional electronic design automation (EDA) simulation.

Millimeter wave (mmWave) technology promises unprecedented capacity and ultra-low latency for wireless communications. However, mmWave systems confront challenges, including high costs, power consumption, and accurate carrier synchronization, significantly limiting mmWave-based applications. The emerging over-the-air modulation (OTAM) technique has recently demonstrated cost-effective and low-power mmWave communication by utilizing channel attenuation difference characteristics to achieve an ASK-like modulation effect. Despite these advancements, the wireless beam modulation (WBM) system based on the OTAM technique suffers from nonlinear interference caused by random phase offsets when supporting multi-node spatial division multiplexing (SDM) access. To address the challenges, we propose a moment-based analysis (MBA) framework to reduce carrier synchronization requirements, enabling the WBM system to linearize nonlinear spatial interference under coarse carrier synchronization. Within the MBA framework, we further develop a moment-based interference cancellation (MBML-IC) algorithm based on the maximum likelihood criterion. The MBML-IC algorithm eliminates interference in the energy domain, thereby supporting multi-node SDM access for the WBM system. Simulation experiments validate the performance improvements regarding the system bit error rate (BER). Besides, the proposed MBA framework and MBML-IC algorithm empower the WBM system to employ lower-precision, cost-effective, and low-power mmWave components, enhancing energy efficiency.

Beam tracking is an essential procedure in millimeter Wave (mmWave) communication systems for providing reliable and robust service. However, beam tracking is a challenging task due to dynamically unpredictable channels. In this paper, we propose a Channel Charting (CC) based beam tracking algorithm to provide robust communication service with low beam search complexity. By projecting the beam direction information to the beam feature domains, the beam tracking problem is transformed into the search of the beam cluster in the beam feature domains. Since the channel chart enables clustering of high-dimension Angles of Arrival (AoA) and Angles of Departure (AoD) to low-dimension beam domains regardless of geographic location, the search complexity is significantly reduced. Furthermore, the neighborhood search algorithm can be applied to obtain the optimal features. The proposed method reduces the search times about 50% in simulation work, with the average tracking accuracy of 98.27%. We also perform the field tests, the results show a high similarity to the simulation. The proposed method exhibits low search complexity with high tracking accuracy in the real scenario.

With the explosive growth in processing and data storage capability, computing in memory (CIM) technology is considered a feasible method to mitigate the memory wall. Re-cently, a floating-gate field-effect transistor (FGFET) technology with single-layer MoS2 channel was proposed, which can flexibly transfer the memory and logic gate by setting the corresponding voltage. In this paper, based on the new FGFETs devices, we propose a hardware-efficient reconfigurable logic-in-memory (LIM) circuit to perform neural network (NN) computing. We first represent the basic FGFET array as a matrix form. Thereby, the adders, multipliers, registers, and PE units are designed by the matrix function of the arrays. The proposed circuits can dynamically transfer the memory to computing logic online when fewer data are required to be stored. A theoretical experiment based on the VGG16 network exhibits an efficiency increase of 85.35% in the same logic area compared with the traditional method.

Due to the open nature of wireless communication, malicious electromagnetic jamming has long been a severe threat to the establishment and stability of communication links. To address this anti-jamming problem, a Markov decision process (MDP) with a two-dimensional action space consisting of transmit frequency and power is proposed in this paper, modeling the interaction between a normal communication link and the presence of malicious jammers in a frequency hopping (FH) communication system. Furthermore, we also prove the existence of the deterministic optimal policy of the proposed model theoretically. To obtain a policy for the communication link to avoid being jammed, the Dual Action Network-Based Deep Reinforcement Learning Algorithm, and Action Feedback Mechanism are proposed. The energy consumption and frequency switching overhead are considered and evaluated in both the proposed model and the algorithm. Finally, the proposed model and algorithm are verified not only in a virtual simulation environment but also in the field testing environment. The result suggests that the proposed algorithm is of great practical value for solving anti-jamming problems.

Service migration, determining when, where and how to migrate the ongoing service, is of paramount importance in mobile edge computing (MEC) for provisioning high quality of service to mobile users. With respect to high network dynamics and stringent delay requirements, service migration is a rather challenging issue in MEC. In this paper, we formulate service migration as a partially observable Markov decision process (POMDP) based on the fact that an edge server can only obtain partial users' information, or the information of its own serving users. A learning-based intelligent service migration algorithm, named iSMA, is proposed to minimize the long-term service delay of all users. iSMA consists of two function modules, a latent space model and a cross-entropy planning algorithm, where the latent space model is used to infer the full state of the environment based on the partial information observed, and the cross-entropy planning algorithm is used to search the best service migration strategy. Numerical results show that our proposed iSMA reduces the service delay by about 58% when compared with a well-known deep learning-based solution.

The millimeter wave (mmWave) communication is envisioned as a key essence of the 6G network to supply high data rate transmission. Nevertheless, both the power consumption and the hardware cost of the mmWave communication system are far beyond the capability of Internet of Things (IoT) devices. The emerging of over the air modulation (OTAM) based mmWave communication technology, i.e., wireless beam modulation (WBM), provides a new perspective to support the low-cost mmWave transmission for IoT devices. However, since the OTAM-based transmission is energy-based detection without phase information, the interference cancellation will be a major challenge for the phase-less receiver. In this paper, we propose three phase-less interference cancellation algorithms named Time Division Multiplexing based Interference Cancellation (TDM-IC), Code Division Multiplexing based Interference Cancellation (CDM-IC), and Code Matching Interference Cancellation(CM-IC) according to the multiplexing methods of the pilot. The three methods perform different characteristics in terms of complexity, robustness, supporting different accessing methods. By employing the proposed interference cancellation methods, the error floor of WBM BER performance is eliminated, which paves the way for the massive connectivity of OTAM based systems.

Strangers build trustworthiness through reputation systems in various online platforms. A reputation system collects history ratings from users about an object/entity and aggregates them as a reputation score, for the reference of future potential users. The reputation score can accurately reflect the real quality of this object if all the ratings are fairly provided, otherwise it may mislead other users if the ratings are unfairly provided. In order to mitigate the impacts of unfair ratings, many unfair rating detection models have been studied in the recent years, through identifying and filtering out the unfair ratings. In this work, we aim to investigate the existing unfair rating detection models considering realistic application settings in an interactive approach where the process of the unfair ratings detection is conducted by involving the interactions between the application system designer and these models. Based on this idea, we design a customized interactive system (CIS) which can satisfy the customized demands of application system designers through five customized functions, i.e., customized scenes, customized attack, customized model, customized metrics, and customized result presentations. After a series of interactions, application system designers can obtain the detection model that best fulfills their demands and the corresponding optimal parameters. To present the applicability of the proposed CIS system, we analyze several typical reputation models in our experiments and the experimental results indicate that our work can effectively bridge the existing unfair rating detection models with realistic applications.

For the sixth-generation (6G) communication, it is required to support the massive Internet of Things (IoT) devices with high data rate applications such as vision-based sensors. Unfortunately, the current sub-6-GHz band is already congested, and lower-band communication is hard to support the high data rate transmission. The millimeter-wave (mmWave)-based communication technology is a promising solution to support the high rate transmission in a new band. However, the high power consumption and hardware cost of the mmWave communication system violates the low-cost design principle of IoT devices, which is a heavy burden for the mmWave application on IoT. In this work, we propose the multiple IoT nodes access-based wireless beam modulation (WBM) technology for the mmWave transmission, where the WBM employs the over-the-air modulation to achieve the low-cost mmWave hardware design with hundreds of megabit per second transmission. To support multiple IoT nodes access, we first design a hyper grant-based and grant-free protocols to achieve the balance between robustness and low latency access. The multiple beam search method is proposed to accelerate the beam alignment process. The channel estimation of WBM is achieved by the pilot detection and beam estimation process, where an iterative pilot cancelation beam estimation method is proposed. According to the simulation and hardware implementation results, the WBM-based communication system can provide a much higher data rate transmission service than the current IoT-based communication systems, and much lower power consumption and hardware cost than the mmWave-based system.

Deep convolutional neural networks (DCNNs) have achieved state-of-the-art performance in classification, natural language processing (NLP), and regression tasks. However, there is still a great gap between DCNNs and the human brain in terms of computation efficiency. Inspired by neural synaptic plasticity and stochastic computing (SC), we propose neural synaptic plasticity-inspired computing (NSPC) to simulate the human brain's neural network activity for inference tasks with simple logic gates. The multiplication and accumulation (MAC) is transformed by the wire connectivity in NSPC, which only requires bundles of wires and small width adders. To this end, the NSPC imitates the structure of neural synaptic plasticity from a circuit wires connection perspective. Furthermore, from the principle of NSPC, we use a data mapping method to convert the convolution operations to matrix multiplications. Based on the methodology of NSPC, fully-pipelined and low latency architecture is designed. The proposed NSPC accelerator exhibits high hardware efficiency while maintaining a comparable network accuracy level. The NSPC based DCNN accelerator (NSPC-CNN) processes DCNN at 1.5625M images/s with a power dissipation of 15.42 W and an area of 36.4 mm2. The NSPC based deep neural network (DNN) accelerator (NSPC-DNN) that implements three fully connected layers DNN consumes only 6.6 mm2 area and 2.93 W power, and achieves a throughput of 400M images/s. Compared with conventional fixed-point implementations, the NSPC-CNN achieves 2.77× area efficiency, 2.25× power efficiency; the proposed NSPC-DNN exhibits 2.31× area efficiency and 2.09× power efficiency.

The hybrid beamforming system based on phase shifters and antenna array can achieve excellent communication performance by the high bandwidth and mutually orthogonal beams of the millimeter wave (mmWave). However, existing beam searching has high computational complexity and is energy-hungery. Besides, the phase shifter arrays in the mmWave system are costly and are not suitable for the internet of thing (IoT) devices that can be deployed in large quantities. This paper proposes a new low-cost energy-efficient mmWave communication system based on beam modulation, which utilizes the attenuation characteristics of different clusters of the channel to achieve modulation. The IoT nodes in the proposed system remove the antenna array and phase shifter network and achieve communication without signal modulation, channel estimation, beam searching and beam alignment. The experiment shows that the proposed system is superior to the existing hybrid mmWave communication system in terms of cost and energy efficiency.

Artificial neural networks (ANNs) have gained state-of-the-art results in classification and regression tasks. However, there is still great gap between ANNs and human brain in terms of computation efficiency. In this work, we proposed the neural synaptic plasticity-like computing (NSPC) to simulate the neural network activity for inference task with ultra-simple logic gates. The multiplication of weight in traditional ANNs is transformed by the wire connectivity in NSPC, which requires only bundle of wires without any logics. To this end, the NSPC imitates the structure of neural synaptic plasticity from a circuit wires connection perspective. The proposed NSPC exhibits comparable inference accuracy with low hardware cost. According to the implementation results, the NSPC requires only 28% logic gate resources of conventional ANNs scheme, 114% throughput improvement and 8.454 times better hardware efficiency on the average.

Benefiting from the caching and transcoding capacity, the fog radio access network (F-RAN) has exhibited the promising potential to promote the performance of the adaptive bitrate (ABR) at the fog server. Despite extensive research on ABR algorithms, the joint optimization of bandwidth resource allocation and bitrate selection is a significant and interesting topic to maximize the QoE for all users in F-RAN. However, the joint optimization problem is intractable to be solved by traditional methods according to complex network dynamics and large user preference variances. In this paper, we propose an intelligent adaptive bitrate algorithm (iABR) based on a hierarchical actor-critic (HAC) agent at the F-RAN server to maximize the overall QoE of multiple users. The proposed iABR can perceive user preference and dynamics of wireless communication environment to automatically adjust the bandwidth resource allocation and bitrate selection policy. Simulation results illustrate that the proposed iABR exhibits more satisfying performance on overall QoE for multiple users compared with state-of-art reinforcement learning based ABR algorithm when adopting average bandwidth allocation and greedy bandwidth allocation.

Hybrid beamforming is a promising technology to reduce power consumption and provide high spectrum efficiency for millimeter wave (mmWave) massive multiple-input multiple-output (MIMO) system. However, it is intractable to obtain global optima for similar constrained joint optimization problems by limitation of hardware architecture. In this work, we proposed a constrained deep neural network (constrained-DNN) based hybrid beamforming for mmWave massive MIMO system, which employs neural networks to replace the beamforming matrices in traditional hybrid beamforming to achieve end-to-end autonomous hybrid beamforming. Traditional hybrid beamforming optimization problem is transformed into a neural network optimization problem, which break the limitation of non-convex optimization. We also present numerical results on the performance of the proposed algorithms, which exhibits significant improvement on bit error rate (BER) performance compared with existing hybrid beamforming schemes.

Recently, as the development of artificial intelligence (AI), data-driven AI methods have shown amazing performance in solving complex problems to support the Internet of Things (IoT) world with massive resource-consuming and delay-sensitive services. In this paper, we propose an intelligent resource allocation framework (iRAF) to solve the complex resource allocation problem for the collaborative mobile edge computing (CoMEC) network. The core of iRAF is a multitask deep reinforcement learning algorithm for making resource allocation decisions based on network states and task characteristics, such as the computing capability of edge servers and devices, communication channel quality, resource utilization, and latency requirement of the services, etc. The proposed iRAF can automatically learn the network environment and generate resource allocation decision to maximize the performance over latency and power consumption with self-play training. iRAF becomes its own teacher: a deep neural network (DNN) is trained to predict iRAF's resource allocation action in a self-supervised learning manner, where the training data is generated from the searching process of Monte Carlo tree search (MCTS) algorithm. A major advantage of MCTS is that it will simulate trajectories into the future, starting from a root state, to obtain a best action by evaluating the reward value. Numerical results show that our proposed iRAF achieves 59.27% and 51.71% improvement on service latency performance compared with the greedy-search and the deep Q-learning-based methods, respectively.

In this paper, we propose an intelligent parking management system by using mobile edge computing (MEC). The proposed system contains vehicle detection, vehicle plate binding and information uploading three processes, which are performed by magnetic sensor edge and gateway edge. Hence, it is critical to design an efficient communication and computing allocation strategy to minimize the power consumption for the power limited device. In this work, we first map the parking management system to a mobile edge computing model and covert the offloading strategy to an optimization problem. By solving the optimization problem, the system efficiency is improved significantly. According to the results, the MEC-based optimized solution can most save 58.52% power dissipation, 99.20% transmission cost or 62.48% latency compared with the cloud computing based method.

Nonorthogonal multiple access technology has been proposed for use in 5G communications systems. In particular, the sparse code multiple access (SCMA) scheme is believed to be one of the most promising techniques among the various nonorthogonal approaches that have been investigated. In this letter, we focus on reducing the complexity of SCMA decoding and we propose a Monte Carlo Markov Chain (MCMC) based SCMA decoder. Benefiting from the linearly increasing complexity of the MCMC method, the proposed SCMA decoder has only 10% of the computational load compared to previous state-of-the-art methods when the codebook size is 64. Consequently, the MCMC SCMA decoder has great potential for use in practical system implementations.

In this paper, we design a hardware and energy-efficient stochastic lower-upper decomposition (LUD) scheme for multiple-input multiple-output receivers. By employing stochastic computation, the complex arithmetic operations in LUD can be performed with simple logic gates. With proposed dual partition computation method, the stochastic multiplier and divider exhibit high computation accuracy with relative short length stochastic stream. We have designed and synthesized the stochastic LUD with CMOS 130-nm technology. According to the postlayout report, the hardware efficiency of the stochastic LUD is as high as 1.5× compared with the exiting LUD methods, and the energy efficiency is also higher than the state-of-the-art LUD when the matrix dimension is 8 × 8 and larger.

In this paper, we propose a hardware-efficient mixed generalized high-radix (GHR) reconfigurable fast Fourier transform (FFT) processor for long-term evolution applications. The GHR processor based on radix-25/16/9 uses a 2-D factorization scheme as the high-radix unit and a 1-D factorization method as the system data routing technology. The 2-D factorization scheme is implemented by an enhanced delay element matrix structure, which supports 25-, 16-, 9-, 8-, 5-, 4-, 3-, and 2-point FFTs. Two different designs were implemented. One design (called discrete Fourier transform core) supports 34 different transform sizes from 12 to 1296 points, while the other design (called FFT core) supports five different power-of-two sizes from 128 to 2048 points. The 1-D factorization method is performed by a coprime accessing technology, which accesses the data in parallel without conflict using a RAM. The GHR combines 2-D and 1-D factorization techniques and improves the throughput by a factor of two to four with comparable hardware cost compared with the previous designs. The speed-area ratio of the proposed scheme is nearly two times better than that of previous FFT processors. Application-specified integrated circuit implementation results based on a 0.18-μm technology are also provided.

In this paper we propose a high performance bidirectional path preserving trellis search (PPTS) detector for multiple-input-multiple-output (MIMO) systems. The error analysis between single direction and bidirectional PPTS detector is given. We prove that the bidirectional PPTS detector can minimize the detection error effectively. Moreover, the proposed detector saves 10% hardware cost with a 0.1 dB Frame Error Rate (FER) gain compared with traditional PPTS detectors.

In this paper, we propose a Sliding Window Method (SWM) to calculate absolute value based on the stochastic computing. We prove that the absolute value of the stochastic stream can be obtained from the limiting distribution of the Markov chain by establishing a Markov model of SWM. The proposed schemes can be employed to both unipolar and bipolar stochastic streams. The simulation and design reports show that the hardware efficiency of the proposed stochastic absolute value calculator is as four times as existing methods.

In this paper, we apply adaptive-signal processing in the reduced precision redundancy filter design for the voltage scaling (VOS) application to achieve high energy efficiency and high SNR performance. RPR technique can mitigate the soft error caused by VOS in the critical path, but the SNR performance of RPR is limited. Thus, we combined RPR and adaptive signal processing to achieve high SNR and low power consumption performance simultaneously for VOS applications. The adaptive signal processing is used to recover the middle significant bits in the result of the filter. From case studies, we find that the proposed method can obtain up to 64% energy reduction with much less SNR performance degradation losing than the traditional RPR and its optimization schemes.

In this paper, we proposed a novel Finite Impulse Response Filter based on stochastic logic referred as SFIR. The proposed SFIR only requires the wire selecting scheme without any logic gate resource. We first map the FIR function to stochastic computation domain. The FIR function is implemented by the wire selecting (WS) method which only requires wire interleaving. Hence the SFIR can achieve ultra high throughput and low cost when apply in the stochastic based system. The SFIR with backward conversion module also has lower hardware cost than traditional method under a given quantization width, which can apply in the low SNR required system and the error tolerant system.

In this letter, we propose a high throughput stochastic Low Bits Computation (LBC) turbo decoder. We represent the signal by a 3-bits width stochastic stream, which improves the accuracy of stochastic computation significantly. We have designed and synthesized our design based on CMOS 90 nm technology. The report shows that the proposed decoder can achieve 4.0 Gbps with 7.1 M gate count to decode a 2048-length R=1/3 turbo code, when the bit error rate (BER) is 10-5@ Eb/N0=1.25 dB.

In this paper, we apply the voltage overscaling (VOS) technique to the residue-number-system (RNS)-based digital signal processing system for achieving high energy efficiency. To mitigate the soft errors caused by VOS, we propose a new method, called joint RNS-RPR (JRR), which is the combination of RNS and the reduced precision redundancy (RPR) technique. The JRR technology inherits the properties of RNS, including shorter critical path, low complexity, and low power. Moreover, JRR can achieve higher power reduction than RNS for VOS applications. Since the soft errors caused by VOS lead to significant performance degradation of RNS, we use the information from RNS and RPR to achieve a high recovering probability of the soft errors with low hardware complexity. From the case study of finite impulse response (FIR) filter design based on the 0.25- μm 2.5-V CMOS technology, we find that JRR can save 62% more energy compared to the traditional FIR with a less than 2-dB signal noise ratio performance loss. We also find that JRR has lower complexity and better performance than the traditional soft error mitigation methods.

In this paper, we proposed a low power digital signal processing (DSP) scheme with stochastic logic protection. The reduction of supply voltage will reduce the power consumption effectively. However, the timing violation will be happened when the voltage overscaling (VOS) is applied. Fortunately, the stochastic logic has simple hardware structure, and the critical path is short. Thus, we can use stochastic logic as the error control (EC) module to mitigate the soft error by the VOS. Compared with traditional EC based low power DSP, the proposed method can achieve higher energy efficiency with high performance. According to the case study of a 26-tap FIR filter, the stochastic logic based EC module can achieve 65% power saving within 2.5dB signal-to-noise ratio (SNR) loss, which outperforms 6dB than traditional RPR method. When the soft error for each logic gate is considered, the advantage of SFIR based system is more obvious than traditional method.

In this paper, we propose a high throughput and hardware efficient Fast Fourier Transform (FFT) architecture for Long Term Evolution (LTE) application. The proposed enhancement delay element matrix (EDEM) which contains the mixed radix unit supports 25, 16, 9, 8, 5, 4, 3 and 2-point FFTs. The reuse technology is also applied into EDEM to reduce the hardware resource. The EDEM reduces the computation cycles significantly since the high radix decomposition method is applied. Compared with the stated of art technology, the proposed scheme improves 2×~4× throughput rate with comparable hardware cost. For all of the 35 FFT lengths in LTE applications, the computation cycles of proposed method are less than the length of FFT, which can supports the continuous flow of processing data in the same clock domain with I/O data. The speed-area product factor outperforms 2~3 times than the existed FFT processor. The proposed architecture also supports the variable length FFT.

This paper proposes a Sliding Window Method (SWM) for stochastic Low Density Parity Check (LDPC) decoder designing. The SWM is formulated for solving the latch-up problem in the Variable Nodes (VN) information updating. The bit in the latch-up state is evolved from the information bit in the sliding window. Then, an optimized hardware structure is proposed for SWM. Compared with traditional VN structure, the SWM require about 35% less hardware resources to achieve the same BER performance.