The design of combinational logic networks is considered in which equivalent or indistinguishable stuck-type faults are confined to a small region of the network. A general type of fault equivalence called S-equivalence is introduced, which defines fault equivalence with respect to an arbitrary set of modules S. A network N is called totally fault locatable with respect to module set S, denoted TFLS, if all specified faults in N are S-equivalent. Some general structural properties of TFLS networks are derived. The problem of designing TFLS networks is investigated for S = {AND, OR, NAND, NOR, NOT} denoted AON, and S = {AON, EXCLUSIVE- OR} denoted AONE. All equivalent fault classes in TFLAON and TFLAONE networks can be identified by inspection. It is shown that every function has a TFLAONE network, that is, a realization where all equivalence classes can be identified by inspection, containing at most one control point or extra input. A method for constructing a TFLAONE realization of an arbitrary function is presented using at most one control point.

The properties of combinational logic functions and networks that influence equivalence among stuck-type faults are investigated. It is shown that the equivalence of certain types of faults depends only on the function being realized. For instance, the fault classes among primary input/output faults are of this type. It is shown that every irredundant realization of the two-variable EXCLUSIVE-OR function has a unique set of ten fault classes. A fault class F in a module M contained in a network N is called intrinsic, if F can be determined from M alone, i. e., F is independent of N. Using the concepts of intrinsic equivalence and inversion parity, conditions for the equivalence and nonequivalence of two fault classes are obtained. These results are applied to the problem of equivalence identification in two-level logic networks where they provide a substantial reduction in the amount of computation required.

Two techniques are discussed for partitioning logic circuits to maximize the resolution of stuck-line faults. One technique exploits the inherent fault resolution of the circuit by attempting to force equivalent faults into the same module. The other involves inserting control points to separate members of equivalent fault classes, a technique called fault class splitting. Some new methods for identifying equivalent faults are also presented.