As the process technology advances, reducing the leakage power as much as possible is one of the utmost challenging tasks in chip implementation. Utilizing cells with multi-VT (threshold voltage) is known to be a very effective method for optimizing leakage power under timing constraints. However, for the sequential cells on the timing critical paths in circuits, there is no easy way for the multi-VT method to reduce the leakage power unless timing is not sacrificed. To overcome this barrier, we introduce a set of new standard cells called hybrid-VT flipflop cells, each of which is implemented with two different VT types, one implanted onto its master latch while the other onto its slave latch, by which the setup time and clock-to-Q delay can be controlled individually and independently. We confirm that applying our power recovery method utilizing hybrid-VT flipflop cells to the benchmark circuits, which have already been optimized by the conventional multi-VT cells, is able to further reduce the leakage power by 8.97% with no timing degradation.

High frequency supply voltage droops make serious operating voltage shift and various reliability issue. For voltage droop mitigation, this paper propose novel on-chip digital dynamic power monitor (DDPM) and droop mitigation system. This dynamic power estimation method use accurate linear regression based model by clock gating signals. In addition, we present a 5nm mobile processor integrates a digital dynamic power monitor based an adaptive clocking system. The DDPM predicts dynamic power per every clock cycle and find large di/dt using clock gating signals. Comparing to simulation, a mean error is less than 1.5%. Furthermore, the DDPM interfaces with a adaptive clock controller to dynamically change the clock frequency in response to large power slope, operating voltage of processor reduce max [email protected] (6.8% dynamic power reduction).

A supply voltage droop, temperature variation and aging effects can generate timing failures during operation. Various adaptive clocking methods have been introduced to resolve the problems. They use a tunable clock to avoid the timing failures rather than using wide design guard bands. However, the system performance analysis becomes complicated in a multi-core system with the adaptive clocking method. In this paper, a queueing theory based system level performance model is proposed to estimate an average response time and power by a closed form equation. Furthermore, for multi-core system with the adaptive clocking, an optimal job scheduling method using the inequality of arithmetic and geometric means is proposed. The proposed optimal job scheduling method relieves a system performance degradation arising from the adaptive clocking. The proposed performance model can analyze the system level performance within ~3% error compared with a JMT system simulation tool. Experimental results also show that the proposed job scheduling method can obtain a significant performance enhancement than the conventional round-robin method.

Accurate in-situ monitoring is urgently required for an adaptive performance control system and post silicon validation. For accurate in-situ monitoring, a direct probing method is presented in which monitors directly measure a path delay from real critical timing paths. However, we may not be able to predict when the timing slack monitors would activate since the activation depends on a design structure and input patterns. If a timing slack monitor is rarely activated by timing critical paths, the observability from this monitor would be low and the monitor possibly can be discarded. For this reason, we propose a novel timing slack monitoring methodology based on switching probability of timing critical paths. Switching probability and correlation on critical timing paths are formulated, and the proposed method finds a list of critical path endpoints for the timing slack monitor insertion under given power and area constraints. Experimental results with ISCAS'89 circuits show that, compared to the method which places monitors for all worst critical paths, 16.67 ~ 97.2% of timing slack monitors are removed and 32.56 ~ 96.88% of dynamic power reduction from the monitors is achieved by the proposed method.

State-of-the-art process technology offers ultra-low power devices operating at ultra-low voltages. However, they show a considerable level of non-linear characteristics. Hence, the accuracy of cell delay and variation modeling for logic cells is expected to be very low with a linear interpolation. In this paper, we propose a compressive sensing based high non-linear cell delay and variation modeling. This paper introduces accuracy optimization methods to fit the delay and variation modeling by pre-processing. Pre-processing is a hybrid approach combining a linear interpolation and compressive sensing for accurate restoration with using less samples. With FinFET cell delay and variation modeling, the experimental results show that the proposed method can obtain a similar or better accuracy with a half of measurement samples than a conventional linear interpolation based modeling.

The optimization of cells and cell combinations used in design is critical to enhance the performance. If frequently used cell combinations are known in advance, a new cell development can be significantly optimized using the cell combinations for chip design. However, extracting frequent cell combinations is an NP hard problem. We propose a new framework, referring as AFSEM, to extract frequent cell combinations for design optimization. To solve this problem, we use a frequent subgraph mining method which is a process of discovering subgraphs. We present an advanced graph modeling and optimized frequent subgraph mining platform for a practical use. The experimental results with various designs demonstrate that the proposed method can discover various types of subcircuits for design optimization with various runtime optimization methods.

Recently, offshore plants are demanded to secure natural resources more and more and it is strongly required unmanned ones for safety of human operators and less running costs. In this paper, a practical multi-user teleoperation system is proposed for monitoring, inspection, operation, and maintenance of the unmanned offshore plants. The proposed system is developed to control mobile manipulator in a cooperative way among multiple human operators for better performance. For this, two control schemes, hand-eye coordination and disjoint axes were introduced for easier intuitive control of the mobile manipulator and for better cooperative control among multi-user, respectively. A well-known passivity-based approach, the time-domain passivity approach was, in addition, adopted to maintain system stability. And then, the proposed multi-user teleoperation system was evaluated via a human-centered method with several quantitative metrics regarding task completion time and interaction forces. Experimental results showed that the proposed multi-user teleoperation system has the benefit in tasks requiring less task completion time and interaction forces.

As CMOS devices become smaller, the process variations (PVs) and aging variations (AVs) become major issues for circuit reliability and yield. In this paper, we analyze the effects of PVs on aging effects such as hot carrier injection (HCI) and negative bias temperature instability (NBTI). Using Monte Carlo-based transistor-level simulations including principal component analysis, the correlations between PVs and AVs are considered, by which the accuracy of analysis is improved (1.2% for standard deviation and 1.7% for Vth99%) compared to other methods that ignore the correlations, especially in the smaller technology. In addition, we perform regression analysis with various models to improve the efficiency of variation-aware aging analysis. All models show an error rate about 1% for NBTI, and quadratic and custom models show an error rate of about 10% on average for HCI.

As CMOS devices become smaller, process and aging variations become a major issue for circuit reliability and yield. In this paper, we analyze the effects of process variations on aging effects such as hot carrier injection (HCI) and negative bias temperature instability (NBTI). Using Monte-Carlo based transistor-level simulations including principal component analysis (PCA), the correlations between process variations and aging variations are considered. The accuracy of analysis is improved (2-7%) compared to other methods in which the correlations are ignored, especially in smaller technologies.