This paper presents a low-complexity design for generating the sigmoid function based on a novel piecewise linear approximation. We have proposed an iterative algorithm to break the whole argument space into the minimum number of intervals, for any given desired accuracy. The LUT address generator of the proposed design does not require any comparators since the breakpoints generated by the proposed algorithm contain only a few non-zero bits. Similarly, the slopes of the line segments are represented by a few non-zero bits, such that the multiplication with slope is realized using hardwired shift operations or a few shift-add operations without using any LUT to store the slope values and without using any conventional multiplier. For the computation of the sigmoid function with fractional accuracy of 7 bits, the proposed design involves only 6 line segments, which requires 2 adders and an LUT to store 6 intercept words. When implemented on an Xilinx Kintex-7 FPGA device, it is found to be 8 times faster than the fastest of the existing designs for the same accuracy and consumes less than half the resources used by the latter. Moreover, the proposed design for 9-bit fractional accuracy is approximately twice as fast and more resource-efficient than a recently reported design offering the same level of accuracy.

In this paper, a new approach to the design of a micro-rotation set for scale-free CORDIC is proposed. The sine and cosine functions of all the micro-rotation angles are realized by a simple shift or a shift-add operations which significantly reduces the hardware complexity. Besides, the micro-rotation set (except the first one) is designed to form mutually exclusive pairs. As a result of mutually exclusive micro-rotations, it is possible to reduce the required number of iterations to almost half for a given precision. Apart from that, the latency, as well as, the hardware complexity are also significantly reduced. A 9-bit fractional accuracy is obtained with just 5 iterations as against 13 iterations required by the conventional CORDIC. Suitable threshold angles are proposed to decide, using low-complexity comparators, whether a micro-rotation should be executed in a given iteration or can be skipped. The proposed circuits to determine the rotation conditions for different iterations involve either 2-bit or 3-bit comparators. The CORDIC circuit based on the proposed set of micro-rotations is shown to converge for any given angle of rotation. Furthermore, the proposed design involves significantly less logic, computation time, and latency than the best of the scale-free CORDIC circuits. When implemented on Xilinx FPGA (Field Programmable Gate Arrays), it requires 20% less area, offers higher operating frequency, and saves close to 19% power and 20% energy per computation over the latter.

In this study, the authors propose a simple yet tighter approximations for the special two‐dimensional Gaussian Q functions using the Trapezoidal rule of numerical integration. This enables a simplified and accurate symbol error probability (SEP) approximation of the hexagonal‐quadrature amplitude modulation (HQAM) in additive white Gaussian noise channel. The proposed approximation further simplifies the SEP calculation of HQAM in parametric , , and fading distributions. Also, the SEP of HQAM over log‐normal shadowing is calculated in this study. The accuracy of the analytical framework is verified using computer simulations.

This brief presents the key concept, design strategy, and implementation of reconfigurable coordinate rotation digital computer (CORDIC) architectures that can be configured to operate either for circular or for hyperbolic trajectories in rotation as well as vectoring-modes. It can, therefore, be used to perform all the functions of both circular and hyperbolic CORDIC. We propose three reconfigurable CORDIC designs: 1) a reconfigurable rotation-mode CORDIC that operates either for circular or for hyperbolic trajectory; 2) a reconfigurable vectoring-mode CORDIC for circular and hyperbolic trajectories; and 3) a generalized reconfigurable CORDIC that can operate in any of the modes for both circular and hyperbolic trajectories. The reconfigurable CORDIC can perform the computation of various trigonometric and exponential functions, logarithms, square-root, and so on of circular and hyperbolic CORDIC using either rotation-mode or vectoring-mode CORDIC in one single circuit. It can be used in digital synchronizers, graphics processors, scientific calculators, and so on. It offers substantial saving of area complexity over the conventional design for reconfigurable applications.

This paper presents reconfigurable CORDIC (Coordinate Rotation Digital Computer) architectures which can be configured to operate either for circular or hyperbolic trajectories in rotation as well as vectoring-modes. We propose three reconfigurable CORDIC designs: a reconfigurable rotation-mode CORDIC that operates either for circular or hyperbolic trajectory, a reconfigurable vectoring-mode CORDIC for circular and hyperbolic trajectories, and a generalized reconfigurable CORDIC that can operate in any of the modes for both circular as well as hyperbolic trajectories. The reconfigurable CORDIC can perform the computation of various trigonometric and exponential functions, logarithms, square-root, etc. of circular and hyperbolic CORDICs using either rotation-mode or vectoring-mode of operation in one single circuit. It can be used in digital synchronizers, graphics processors, scientific calculators and many other applications, with significant area saving over that of using two CORDICs for different trajectories.

Filtering is one of the most important modules in signal processing paradigm. This study presents a field‐programmable gate array implementation of various window functions using coordinate rotation digital computer (CORDIC) algorithm to minimise area‐delay product. First, the authors modify the Taylor series approximation order used in the scaling‐free CORDIC, to completely eliminate the scale‐factor and, yet, preserve the range of convergence spanning across the entire coordinate space. Secondly, the authors propose a new generalised technique for micro‐rotation sequence identification to reduce the number of iterations required by the pipelined CORDIC processor. Then, this circular CORDIC processor is used to realise window functions. The existing window architecture uses a linear CORDIC processor in series with circular CORDIC processor, resulting in long pipeline. The authors replace the linear CORDIC with multiple optimised shift‐add networks to reduce area and pipeline depth. As a result, the proposed window architecture, on an average requires approximately 64.34% less pipeline stages and saves up to 48% area. The authors have designed the processor to implement Hanning, Hamming and Blackman window families. The implementation of the proposed architecture is detailed in this study.

The COordinate Rotation DIgital Computer (CORDIC) algorithm is a famous technique for realizing complex arithmetic functions using simple shift-add operations. This paper presents a novel completely scaling-free CORDIC algorithm in rotation mode for high performance hyperbolic computations. We target algorithm level improvements to achieve low area and power-delay product on FPGA. Instead of complex search algorithms, we use the most significant one bit detection technique for micro-rotation sequence identification, which helps in significantly reducing the number of pipelining stages. The proposed technique uses mathematical identities to extend the range of convergence. The eight-staged pipelined architecture implementation requires a ROM in the preprocessing unit for storing the initial coordinate values, while the ROM for storing the elementary angles is eliminated. The FPGA implementation of the proposed processor requires 46.35% less gates and has 31.81% less delay when compared with Xilinx Core IP-CORDIC v3.0. Moreover, on an average it consumes 75.96% less power when compared with Xilinx CORDIC v3.0. Hence, the proposed technique provides an area–power-delay efficient VLSI implementation for calculating hyperbolic functions and exponents. The detailed algorithm design, along with FPGA implementation and area and time complexities, is presented in this paper.

This paper presents an area-time efficient CORDIC algorithm that completely eliminates the scale-factor. By suitable selection of the order of approximation of Taylor series the proposed CORDIC circuit meets the accuracy requirement, and attains the desired range of convergence. Besides we have proposed an algorithm to redefine the elementary angles for reducing the number of CORDIC iterations. A generalized micro-rotation selection technique based on high speed most-significant-1-detection obviates the complex search algorithms for identifying the micro-rotations. The proposed CORDIC processor provides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements. Compared to the existing recursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan XC2S200E device.