Sphere Decoding has become a popular implementation of MIMO decoding due to its improved performance at lower hardware complexity. Present ASIC implementations fail to consider sources of pipelinability and parallelism in the algorithm to achieve reduced power. In this work, we provide a proposal and initial results for an improved architecture which aims to increase overall energy efficiency (b/s/mW) of the decoder. This improvement is based on a novel implementation which combines the use of a deeply pipelined data-path and "multi symbol vector" based approach to exploit the pipeline. Implementation in 0.18μ 1.8V CMOS technology provides an operational frequency of 128/230(retimed)MHz at 409 mW(DFF memory)/ 360 mW(realistic memory) and 3.44 sq.mm (DFF memory).

Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in 3DICs, and the higher temperatures increase delay and leakage power, potentially negating the performance improvement. Thermal vias can help to remove heat, but they create routing congestion, which also leads to longer interconnects. It is therefore very difficult to tell whether or not a particular system may benefit from 3D integration. In order to help understand this trade-off, physical design experiments were performed on a low-power and a high-performance design in an existing 3DIC technology. Each design was partitioned and routed with varying numbers of tiers and thermal-via densities. A thermal-analysis methodology is developed to predict the final performance. Results show that the lowest energy per operation and delay are achieved with 4 or 5 tiers. These results show a reduction in energy and delay of up to 27 % and 20 % compared to a traditional 2DIC approach. In addition, it is shown that thermal-vias offer no performance benefit for the low-power system and only marginal benefit for the high-performance system.