A memory BIST enhancement, ESP short for exercising system paths, is described that allows the efficiency and functional capabilities of standard approaches while addressing two important problems. Conventional Memory BIST techniques require MUXes at the inputs of the memory that allow for the inputs to be driven either by system signals or by test signals. These MUXes add delays, in the system path going to the memory, which often has critical timing. ESP eliminates such delays by implementing the MUXing function 'before' scan cells. ESP also uses scan cells to capture the memory output for feeding back to the BIST controller. This output may have traveled through some logic before getting to the recording scan cells. By including the delays of the system input and output paths, ESP allows for verifying that the memory will work correctly as part of the system rather than just as an isolated unit. Using ESP, a memory BIST can catch transition and delay faults that are impractical, or even impossible, to catch otherwise. Therefore, ESP can be useful for all memories but may be crucial for the memories which cannot tolerate the addition of the MUX delay to functional paths.

Testing nonscan blocks of hardware such as small embedded memories (register files, etc.) can be done using existing scan chains due to the atypically small memory size. FastScan's Macrotest has been developed to solve this problem, and the more interesting problem of concisely and accurately informing the user about the specific hardware and command constraints which prevent successful testing. This allows the user to quickly identify the particular problems, and add DFT or change the patterns to match the architectural and other restraints of the embedding.

Testing of one-dimensional (1-D) unilateral iterative logic arrays (ILA's) of combinational cells with constant test vectors is studied and the concept of one repetition length (ORL) within the tests used for testing C-testable arrays is described. The impact of ORL on the test set size and the design of the test generator are discussed. ORL can dramatically reduce the on-chip test generator size with a negligible increase in the test set size. ORL, coupled with a single distinguishing sequence (DS) for ILA's with cell vertical outputs has proved to be attractive in terms of both reduced test set size and reduced test generator size. ORL testability can be used for C-testable arrays with single faulty cell and multiple faulty cells. The technique for using a single linear finite state machine (LFSM) for generating the necessary deterministic test patterns followed optionally by pseudorandom patterns from the same automaton is discussed. Use of an LFSM as a built-in test generator for only deterministic tests for 1-D ILA's is covered. With ORL, a compact LFSM based built-in self test (BIST) generator can deliver the test vectors to all the cells in the array. The exact probability distribution equation has been developed for additional bits needed to map a nonlinear machine (FSM) definition into a LFSM definition. The distribution clearly shows that the expected number of additional bits is very small, often zero.>

Linear Finite State Machine for One Dimensional (1D) Iterative Logic Arrays (ILAs) is described. The technique for modifying the Linear Feedback Shift Register (LFSR) based test generator called Linear Finite State Machine (LFSM) for deterministic test pattern generation is discussed and extended for generating the test vectors for 1D unilateral ILAs. One Repetition Length (ORL) of C-testable ILAs and unique characteristics of the C-testable test patterns are used for the compact design of the LFSM based at-speed Built-in Self Test (BIST). Such LFSM based BIST occupies small silicon area, simplifies the design of the controller and does at-speed testing of the ILAs. This results in reduced time and cost of testing. In addition, the exact probability distribution equations are developed for additional bits needed to map a Finite State Machine (FSM) into an LFSM. The distribution clearly shows that the expected number of additional bits is very small, often zero. The probability distribution equations are equally valid for any LFSR based test generator for other circuits.>

Testing of one dimensional unilateral iterative logic arrays (ILAs) of combinational cells under multiple faults is discussed. It has been shown that it is possible to generate a test set for ILAs with primary outputs under multiple faults. Some ILAs have a constant number of test vectors independent of the size of the array. These types of arrays are called C-testable arrays. Present work proves that all useful one dimensional unilateral ILAs with only boundary outputs are not C-testable under multiple faults.>

Signal probability calculations are necessary to determine the random pattern testability of logic circuits. Determination of random pattern testability is necessary for considering the use of weighted or unweighted linear feedback shift registers (LFSRs) as an appropriate testing method. This paper presents an algorithm to accurately and efficiently (both in space and time) calculate signal probabilities (sometimes called syndrome analysis) within digital logic networks. It has the advantage that it uses a new method for signal probability calculations which is typically both fast and accurate, and which has already efficiently produced results for all the ISCAS combinational circuits.>

A deterministic test pattern generator for BIST, based on linear feedback shift registers is discussed. A method of designing the test pattern generator in order that it generates deterministic as well as pseudo random patterns is presented. One application of this method is illustrated where deterministic at-speed testing of C-testable ILAs, covering all possible single and multiple combinational faults is achieved. Response analysers are discussed including one with zero aliasing probability. The algorithms for synthesizing the small amount of BIST hardware are explained.>

The nature of many problems related to testability requires detailed information about their underlying test parameters. These parameters are commonly referred to as controllability and observability. This research concerns exact measures of detectability, controllability, and observability to measure the relative importance of the latter two on the likelihood of the former. New functional methods for fault analysis are utilized which allow computations not previously possible; the empirical results presented here are an example of such an application.>