Yesterday's cell phones have rapidly evolved into versatile multi-media computers heavily loaded with a wide spectrum of technologies to support many functions and use modes. Designing and verifying such complex devices becomes increasingly challenging due to the need to: incorporate larger number of functions and diverse use modes, increased bandwidth, provide support for multimedia devices with high resolution, offer new methods for user interactions, and all of this at a fixed power budget and with high reliability. In addition, teams need to keep up with the convergence of wireless radio algorithms and be able to support more functionality moving into the software layer.

Over the past 40 years, the semiconductor industry has exponentially driven cost per function down following the oft stated Moores Law. It is becoming increasingly difficult to scale as we move into the 32nm and beyond process nodes due both to physics and economics. A lower cost alternative method of scaling is becoming more available in the form of vertical chip integration.

This talk will discuss the current state of commercial CAD, and speculate upon how it might evolve in both the near and longer term. In the near term, commercial CAD will concentrate on the familiar problems of the VLSI field - completing larger designs, optimizing yield, coping with variability, and so on. These and similar well known problems, already known to customers and called out in the ITRS roadmap, will keep commercial CAD busy for the next few years.In the long term, however, there are many more possibilities. In particular, fields such as diverse as genetics and nano-technology are currently struggling to produce small but working examples, but have the potential to cheaply build very large and complex systems. As the fabrication technology in these fields matures, designers will need more automated tools, just as they have over the history of IC design. Furthermore, there will surely be large mixed systems containing more than one of these technologies, including the current electronic technology and/or its technological successors. It is therefore possible that the long term evolution of commercial CAD will encompass many fields, with a core competency of the explicit construction of large and complex systems.

This introductory embedded tutorial gives an overview of the design problems at hand when designing integrated electronic systems in nanometer-scale CMOS technologies. First, some general problems that affect circuit design are addressed, such as the increased leakage and variability with scaling technologies. Next, the impact of this on digital circuit design and embedded memories is discussed. Finally, problems bothering embedded analog circuits are presented, such as reducing supply voltages, poor design productivity and signal integrity troubles. Addressing these problems will determine whether the design road ends at CMOS technology marker "65 nm " or not.

The makeup and relationships within the design supply chain are changing rapidly. One-stop shopping, whereby a system house procures most of its design and fabrication services from a single source, is now being supplanted by a host of outsourcing suppliers. These players are developing online integration plat-forms for outsourced design engineering, business transactions, and data management.

Article Free Access Share on Issues and answers in CAD tool interoperability Authors: Mike Murray Acuson, Mountain View, Ca. Acuson, Mountain View, Ca.View Profile , Uwe B. Meding Concurrent CAE Solutions, Santa Clara, Ca. Concurrent CAE Solutions, Santa Clara, Ca.View Profile , Bill Berg Mentor Graphics, Wilsonville, Or. Mentor Graphics, Wilsonville, Or.View Profile , Yatin Trivedi Seva Technologies, Fremont, Ca. Seva Technologies, Fremont, Ca.View Profile , Bill McCaffrey High Level Design Systems, Santa Clara, Ca. High Level Design Systems, Santa Clara, Ca.View Profile , Ted Vucurevich Cadence Design Systems, San Jose, Ca. Cadence Design Systems, San Jose, Ca.View Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996Pages 509–514https://doi.org/10.1145/240518.240615Published:01 June 1996Publication History 1citation373DownloadsMetricsTotal Citations1Total Downloads373Last 12 Months40Last 6 weeks4 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Publisher SiteeReaderPDF