A hybrid sigma converter integrated with a digital low dropout (DLDO) regulator is presented in this paper and designed for high-density power delivery applications. The proposed converter employs an input-series and output-parallel (ISOP) topology, combining a high-side hybrid converter for high power efficiency and a low-side DLDO for rapid transient regulation. An auxiliary control loop minimizes the DLDO’s dropout voltage across wide input and output voltage ranges, eliminating efficiency degradation under non-optimal operating conditions. The converter achieves a peak efficiency of 92%, with a system power density of $101.3 \mathrm{~W} / \mathrm{cm}^{3}$. A $1.6 \mu$ s response time and $\mathbf{3 6 m V}$ voltage droop are achieved with a $\mathbf{2 A}$ load transient.

This paper presents a power-efficient error-feedback and cascaded-integrator-feedforward (EF-CIFF) hybrid noise-shaping (NS) successive approximation register analog-to-digital converter (SAR ADC). A joint dynamic amplifier, comparator and lossless passive summer structure is proposed in the NS SAR ADC, where a pair of capacitors is reused among the above three sub circuits. The capacitors are first employed as the load of the dynamic amplifier, then used to store the residual signal in the summer, and finally used to compose a dynamic-biased comparator. The joint structure and the fully dynamic operations make the NS SAR ADC power-efficient. The ADC is designed in a 40nm CMOS. With a sampling rate of 50MHz, the ADC achieves 81.8dB SNDR over a 3.125MHz BW in simulation. The power consumption is 190.3μW, resulting in a Schreier FoM of 184.0dB.

This paper presents a 1-GS/s 7-bit 3-then-1 bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). To strike a good balance among the noise performance, power consumption, transistor size, and offset, a reconfigurable reference-embedded comparator is proposed. The comparator is first configured with 7 embedded reference voltages, which can complete the conversion of 3 bits in one cycle. The 3-bit/cycle comparator is then reconfigured to 1-bit/cycle in the last conversion cycle, with improved noise performance and reduced the offset mismatches between the seven latches. As a result, the ADC achieves relatively good precision with considerable power efficiency. A design example of 1-GS/s 7-bit SAR ADC in 40nm CMOS technology is presented. Simulation results show that the ADC achieves a spurious free-dynamic-range (SFDR) of 53.98 dB a signal-to-noise-and distortion ratio (SNDR) of 42.51 dB, with a figure-of-merit of 27.3 fJ/conv.-step.

This paper presents a compact ring-oscillator (RO)-based phase-locked loop (PLL) implemented upon the principle that reference oversampling essentially boosts the reference frequency and thus extends the achievable bandwidth to such an extent that an area-efficient RO can be used without significantly sacrificing the phase noise (PN) and jitter performance when compared to conventional LC-based PLLs. By employing an analog reference oversampling PLL structure, RO noise is greatly suppressed by taking advantage of such an extended maximum PLL bandwidth. In conjunction with power- and spur-reduction techniques including a low-power time-multiplexed Gm stage and a capacitive parasitic-proof RO, this work implements a compact and low PN PLL without requiring complicated calibration or additional power/area penalties. Fabricated in a standard$0.18~\mu $m CMOS technology, the proposed PLL occupies an active area of 0.41 mm2. When operating at 1.6 GHz, the proposed PLL achieves an rms jitter of 585 fs with 5.7 mW power consumption, yielding a FoMREFof -240.1 dB.

This paper presents a 7.68MSps 20kHz-BW nested continuous-time (CT) delta-sigma modulator (DSM) analog-to-digital converter (ADC). The nested DSM is composed of an inner analog CT DSM and a weighted multi-threshold MSB-pass quantization path. In the inner analog CT DSM, a negative-R-based cross-RC integrator structure is employed to reduce the resistance by 8×, thus improving area efficiency and alleviating parasitic issues introduced by large standard poly resistors. In the MSB-pass quantization path, several techniques including weighted counting, multi-threshold MSB-pass comparison, look-ahead comparison, and consecutive identical state detection are proposed. These techniques help to double the speed of the proposed nested DSM over the conventional nested DSM. Fabricated in a 180nm CMOS, the prototype DSM achieves SNR/SNDR/SFDR of 108.3dB/107.3dB/121.6dBc, with maximum resistance of only 179kΩ in the loop filter. The measured Schreier figure of merit (FoMS) is 183.6dB.

The Ising machine is regarded as a promising computing architecture for obtaining approximate solutions to some nondeterministic polynomial time hard (NP-hard) problems. Utilizing a CMOS process, a large-scale Ising machine can be integrated to achieve enhanced energy efficiency compared to classical computing approaches. This work presents a fully symmetric, oscillator-based CMOS Ising machine architecture, which employs differential ring oscillator (ROSC) to implement spin, ensuring consistency between the theoretical framework and practical implementation. The coupled ROSC array is mathematically proven to have a Hamiltonian in the form of the Ising model, making it particularly suitable for implementing the Ising machine. A 240-spin CMOS Ising machine has been fabricated and tested. The proposed Ising machine takes a square lattice topology with four-level, reconfigurable coupling parameters with sign. Using a successive approximation sampling scheme, the Hamiltonian can be refined with the increasing iterations. The prototype demonstrates a power consumption of 26.3$\mathrm {\mu \text {W} }$/Spin, indicating significant energy efficiency and performance enhancement.

This paper presents a 4th-order continuous-time$\Delta \Sigma $modulator (CTDSM) employing a 6-bit time-domain quantizer. The implemented quantizer employs a time-to-digital converter (TDC)-based architecture which strikes a good balance among speed, resolution and power efficiency. A novel background calibration technique is proposed to mitigate dynamic inter-symbol interference (ISI) errors in multi-bit digital-to-analog converters (DACs) while introducing negligible additional excess loop delay (ELD), power consumption and circuit complexity. The prototype in a 40-nm CMOS is sampled at 630 MHz, achieving an SNDR/SNR/SFDR/DR of 75 dB / 77.9 dB / 86.6 dBc / 81 dB over a signal bandwidth of 25 MHz. The proposed background ISI error calibration scheme suppresses 2nd- and 4th-order harmonics by 8.5 dB and 3.5 dB, respectively. The total power consumption is 21.23 mW, achieving a Schreier Figure of Merit (FoMs) of 171.7 dB.

A 0.2–2.6 GHz reconfigurable direct conversion receiver is proposed in this article. The receiver’s high-linearity mode and high-gain mode can be configured by either bypassing or including the low-noise amplifier (LNA) stage. An agile-switching module is designed to facilitate the mode transitioning. In high-gain mode, a variable-gain current-reused shunt-feedback (VGCRSF) LNA with radio frequency (RF) gain-adapted impedance matching technique is proposed. Instead of utilizing a shared transconductance (Gm) stage in both the I- and Q-path, the Gm-separated IQ-leakage suppression (GSIQLS) structure is employed in the mixer stage to reduce the complex and frequency-dependent IQ mismatch engendered by the nonideal local oscillator (LO) signal overlap. In baseband, both the gain and the bandwidth are made configurable through the utilization of a bi-quad low pass filter (LPF) and a programmable gain amplifier (PGA). The proposed receiver is fabricated in a 40-nm CMOS technology. Measurement results indicate a maximum conversion gain of 78.5 dB and a minimum noise figure (NF) of 2.5 dB are achieved. The input 1-dB compression point (IP1dB), in-band (IB) third-order input-referred intercept point (IIP3), and out-of-band (OOB) IIP3 are larger than 0, 9.7, and 13.1 dBm, respectively. The gain and phase mismatch of the quadrature receiver are lower than 0.3 dB and 1°, respectively, over the baseband bandwidth ranging from 410 kHz to 24 MHz. The receiver occupies an area of 0.605 mm2 and consumes a power of 75.4 mW.

The sampling noise cancellation (SNC) technique has been applied to noise-shaping SAR (NS-SAR) ADCs to reduce the sampling capacitance, which makes the ADCs more easy-driven. However, the traditional SNC technique limited its applications by the PVT-sensitive noise cancellation ratio and hence noise performance. This paper proposes a new SNC technique with self-calibrated PVT-robust noise-cancellation ratio. The error of the noise-cancellation ratio (NCR) is detected and calibrated in background without any external dither or test signal. Simulation results show that the proposed SNC technique achieves more PVT-stable NCR over a traditional SNC scheme.

This article presents an energy-efficient single-ended transceiver featuring the proposed AC/DC-coupled pre-emphasis feed-forward equalizer (PE-FFE) and edge-dependent phase-modulation decision feedback equalizer (PM-DFE) for low-power memory controllers. Specifically: 1) on the transmitter (Tx) side, an AC/DC-coupled PE-FFE is implemented in a ground-terminated Tx to minimize the equalization (EQ) power and maximize the output swing; 2) on the receiver (Rx) side, an edge-dependent PM-DFE operating on the full-swing signal edges is proposed for time-domain EQ, which improves sampling margin and reduces the linear EQ requirement as well as the power consumption. The design, fabricated in 22-nm CMOS, achieves a data rate of 20 Gb/s/pin with a 41 mV increase in the Tx output eye height and a 0.12 UI increase in the Rx sampling margin over a channel with a 10.3 dB loss. Measurement results reveal an energy efficiency of 0.45 pJ/b and 0.38 pJ/b for the Tx and the Rx, respectively, and a figure-of-merit of 0.081 pJ/b/dB (Tx+Rx).

This paper proposes a look-up-table (LUT)-based background calibration to improve the linearity of the ring voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC). The nonlinearity of the tuning gain$(\boldsymbol{K}_{\mathbf{VCO}})$of the VCO is considered as that there is an individual$\boldsymbol{K}_{\mathbf{VCO}}(\boldsymbol{K}_{\mathbf{VCOI}})$for each ADC output level. The$\boldsymbol{K}_{\mathbf{VCO}}-\mathbf{Locked}-\mathbf{Loop}$(KLL) is employed to force the$\boldsymbol{K}_{\mathbf{VCOI}}\mathbf{s}$to the same reference value, thus eliminating the nonlinearity. The effectiveness of the KLL-assisted linearization scheme is not affected by the matching property of the technology and the characteristics of ADC input signal. Thanks to the KLL-assisted calibration, the total harmonic distortion is suppressed by 37.8dB with the required ADC output samples of 218, achieving a fast linearization process.

This paper presents an energy-efficient single-ended (SE) transmitter (Tx) for memory interfaces, supporting non-return-to-zero (NRZ) and four-level pulse amplitude modulation (PAM-4) dual modes. The dual-mode Tx fully reuses the output driver, allowing high-performance impedance matching at the “/” and “1”/“11” levels of the NRZ/PAM-4 mode, and enabling low-power relaxed impedance matching at the “01” and “10” levels of the PAM-4 mode. The pre-emphasis equalization is proposed with high energy efficiency to enlarge the eye-opening using impedance modulation and a half-rate charge pump for the ground-terminated dual-mode Tx. The five-step three-point impedance (ZQ) calibration with offset cancellation is performed to enhance the level separation mismatch ratio (RLM). Implemented in a 22-nm CMOS process, the Tx achieves the data rate of 16 Gb/s/pin NRZ drawing 8.07 mW over a 12.9-dB loss channel and of 32 Gb/s/pin PAM-4 drawing 6.87 mW over a 4.6-dB loss channel with 99.0% RLM.

This paper presents a 3bit/cycle 1GS/s8-bit SAR ADC with asynchronous ping-pong quantization scheme. With the proposed scheme, settling requirement of the reference voltages for multibit quantizer can be relaxed. In addition, loop-unrolled technique can be easily embedded in the SAR logic for higher speed without extra hardware consumption. Moreover, using the ping-pong scheme, the comparator offset can be corrected in background mode without extra calibration phase. The ADC is designed and simulated in 22nm CMOS process. Without calibration, the ADC achieves 33.4 dB SNDR. With offset calibration, the SNDR can be improved to 47.2 dB.

This paper presents a continuous-time sigma-delta modulator (CTSDM) with a voltage-controlled-oscillator-based (VCO-based) integrating quantizer. A background replica-based calibration technique is proposed to alleviate the impact of the process, voltage supply, and temperature (PVT) variations on the tuning characteristic and current consumption of the VCO-based quantizer. Matching between the replica VCO and the main VCO in the proposed calibration is not needed. A latency-free background calibration technique is also proposed to eliminate the distortions caused by the DAC mismatch. The prototype VCO-based CTSDM is fabricated in a 40 nm CMOS and achieves SNDR/SFDR/DR of 76.4 dB/91.7 dBc/79.6 dB, respectively, within a 50 MHz bandwidth (BW) at 1.6 GHz sampling frequency. The measured SNDR varies within ±1 dB over a temperature range of$0\sim 80~^{\circ }\text{C}$and a voltage supply variation of ±10%, across different tested samples. The power consumption is 18.1 mW, achieving a Schreier Figure of Merit (FoMS) of 170.8 dB.

This paper presents a phase domain excess loop delay compensation (ELDC) technique for voltage-controlled oscillator-based (VCO-based) continuous time (CT) ΔΣ ADC. The ELDC is achieved by shifting the phase of the sampling clock which composes a zero-order feedback loop in phase domain and avoid long latency between quantizer and DAC. The phase shifting is realized by a phase selector which selects the sampling clock from multi-phase clock signals generated by the phase interpolator. To ensure the stability of the ΔΣ ADC, a two-step phase selector is proposed to optimize the latency in the zero-order feedback loop. Simulation results shows that the proposed technique can effectively compensate ELD in phase domain and low latency feature in the feedback loop makes the technique suitable for high speed VCO-based CT ΔΣ ADC.

This paper demonstrates a combination of mm- wave low noise amplifier (LNA) and active vector-modulated phase shifter (VMPS) in 40-nm CMOS technology. System considerations of noise and gain are discussed in detail. Wideband impedance conversion is realized through a passive quadrature hybrid coupler (QHC). A three-coil transformer between the variable gain amplifier (VGA) and LNA is utilized to achieve broadband impedance matching, boost transconductance and broaden the bandwidth. With 8-bit resolution, the achieved minimal root-mean-square (RMS) phase and gain errors are 0.26oand 0.48dB, respectively. The overall power consumption is 139.88mW, while the working peak gain is 17.83dB and the minimal NF is 5.4dB. The proposed PS is simulated to work from 22-GHz to 40-GHz, covering the whole Ka-band. The overall area of the LNA-PS is only 0.266 mm2.

Dynamic amplifiers are favored for the low power consumption feature in applications such as residual amplification, but the temperature-dependent gain variation limits their performance. In this paper, a temperature-compensated common-mode voltage detector is proposed for dynamic amplifiers to maintain performance against temperature variation. The proposed method employs a power-saving negative temperature coefficient reference voltage generator, a switched-capacitor subtractor and a temperature-insensitive inverter based zero-crossing detector to alleviate gain variation. Simulation results show that the proposed method reduces the maximum gain variation from 16.0% to 2.2% in a wide temperature range from -40°C to 125 °C with a frequency-dependent power consumption of only 16.0uW at 250MHz in 40nm CMOS technology.

With the explosive growth of data rate demand, four-level pulse amplitude modulation (PAM4) SerDes standards are emerging, while binary non-return-to-zero (NRZ) standards still take the market. This paper proposes a novel dual-mode architecture designed for SerDes application data rate of up to 56 Gb/s with PAM4 modulation, and compatible to the legacy 28 Gb/s standards with NRZ modulation scheme. Attractively, with minor modification, the same hardware to send PAM4 signal can be used to implement a 28 Gb/s NRZ transmitter with 4-tap forward-feedback equalization (FFE), and meanwhile the PAM4 receiver can be easily reconfigured as a half-rate NRZ receiver with 1-tap loop-unrolled decision-feedback equalization (DFE). In addition, a digital duty-cycle correction (DCC) loop ensures the duty-cycle distortion (DCD) jitter introduced by half-rate transmitter architecture being less than 0.01UI in NRZ mode. The architecture is verified in 22nm CMOS FDSOI technology, and the simulation results across lossy channel show that the serial link transceiver can transmit 28/56 Gb/s with the eye opening of 400 mVpp in NRZ mode, and 150 mVpp in PAM4 mode in 1.2 V supply.

A 28 Gb/s source-series-terminated (SST) transmitter in 22 nm CMOS FDSOI technology is presented. A stacked SST driver embedded with a 2-tap feed-forward-equalizer (FFE) is employed for flexible equalization setting, swing controlling and independent impedance tuning. An optimized precoding technology and closable digital impedance calibration loops are adopted and reduce the power dissipation largely. The equalization result exhibits 8.5 ps total jitter (TJ) and 46 mVpp eye-opening at 28 Gb/s over a 23 dB loss channel. At 0.8 V supply, the implemented transmitter consumes 17.3 mW in total.

A new Injection-Locking Frequency Divider (ILFD) based dual-modulus prescaler with extended locking range is presented in this paper. The tuning capacitor inserted into the ring oscillator loop can widen the common locking range of two operating modes of the prescaler. A dual-modulus prescaler using the proposed method is designed and simulated in a 65nm CMOS process. Simulation results show that the locking range of the divide-by-4/5, from 11.5 GHz to 19.1 GHz, is extended by more than 40 % compared with from 14 GHz to 19.4 GHz using the conventional design.

In this paper, a digital calibration scheme is proposed to correct phase mismatch among the multi-phase inputs of the pulse combiner to suppress the spurs at the output of the multi-modulus fractional frequency local oscillator divider. Compared with the conventional design, the proposed calibration scheme utilizes most correlated comparison algorithm to reduce convergence time significantly. The proposed calibration scheme is implemented by digital logic, and simulation results show that for all division ratios at maximum output frequency of 6 GHz, average convergence time is reduced by at least 68% compared to the conventional design.

the integration of Global Navigation Satellite Systems (GNSS) receiver with other wireless functionalities, e.g., GSM, WCDMA, LTE, Bluetooth, and WiFi, brings up new design challenges due to constrained silicon area and power consumption, and especially the interferences from other wireless functionalities. A dual-channel multi-mode GNSS RF receiver, for reception of GPS-L1, GLONASS-B1, Compass-B1, and Galileo-E1, is proposed to address these challenges. A novel frequency plan and a reconfigurable complex band-pass filter enable the two multi-mode reception channels to share most circuit blocks and thus reduce the power consumption and silicon area. An N-path filter and adaptive gain control is implemented in the RF front-end to reject the out-of-band interferences for high linearity. Designed in a 40nm CMOS, the proposed multi-mode GNSS RF receiver, including the RF front-end, baseband filter and ADC, PLL, and VCO, achieves a total noise figure of 1.7dB, out-of-band (1710MHz) input 1dB compression point of −16.5dBm, while consuming a total power of 13.2mW.

A novel pseudo-differential wideband Low Noise Amplifier (LNA) for DVB-S.2 Radio Frequency (RF) tuners is proposed. Based on narrow-band source degenerated structure, the proposed wideband LNA, covering the Digital Video Broadcast-Satellite.2 (DVB-S.2) band, demonstrates a higher gain and a lower Noise Figure (NF) than traditional wideband LNAs. Furthermore, a pseudo-differential topology is proposed to separate and cancel the in-band interferences. Designed and simulated in a 0.18 um CMOS, the proposed wideband LNA demonstrates an NF better than 2.5 dB and an input matching better than -10 dB with a gain higher than 18 dB over the operating band from 950 MHz to 2150 MHz. The LNA also achieves a typical 30 dB suppression of the interferences from the GSM signals. The simulated input-referred 3rd-order intercept point (IIP3) is 9.45 dBm and the total current consumption is 12 mA from a 1.8 V power supply.

A novel frequency divider for Quantization Noise (QN) suppression in fractional-(QN) phase-locked loops (PLLs) is presented in this paper. The proposed Multi-Modulus Frequency Divider (MMFD) utilizes a novel glitch-free divide-by-0.5/1/1.5/2 cell to reduce the frequency division step to 0.5 and the quantization noise induced by ΔΣ modulation is thus suppressed by additional 6dB. The circuit is designed and simulated in a 0.18μm CMOS process. The maximum input frequency is up to 3.8GHz across all variations of Process, supply Voltage and Temperature (PVT) and the current consumption is about 8mA from a 1.8V supply. Compared with other frequency dividers used for QN suppression, the proposed MMFD achieves 6dB QN suppression while consuming less power and operating at higher input frequency.

A new type Phase Frequency Detector (PFD) and Charge Pump (CP) configuration with extensible linear range is presented in this paper. The proposed Linear Range Extensible PFD and CP (LRE-PFDCP) can minimize the impact of non-ideal effects caused by the limited linear range of the Conventional PFD and CP (C-PFDCP). Thus, the frequency acquisition time of the Phase-Locked Loop (PLL) implemented with LRE-PFDCP can be significantly reduced during large frequency hopping. Unlike other linear range extension techniques, the proposed LRE-PFDCP is robust and does not cause PLL unlocking. The proposed LRE-PFDCP together with a prototype PLL is designed and simulated in a 0.18μm CMOS process. Simulation results show that the PLL achieves 320MHz frequency hopping within 4μs, which is about 3.25 times faster than the same PLL with linear range extension disabled.

A new adaptive calibration scheme for IIP2 in direct down-conversion mixers is proposed for reduced implementation complexity and improved convergence time. The proposed IIP2 adaptive calibration scheme utilizes a modified least-mean-squares (LMS) algorithm with a variable update step and a highly IMD2-correlated reference input. Detailed implementation of the proposed IIP2 adaptive calibration is presented. Simulation results show that the proposed IIP2 adaptive calibration achieves a 40 dB suppression of mixer's IMD2 and a 50 μsconvergence time, which is 100 times faster than that of a conventional LMS adaptive algorithm.