Suh-Juch Lee

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1ranked-venue papers

0as first author

0since 2021 · last 1995

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Electronic design automation · 80% Integrated circuit design · 20%

Topics — the 5 heaviest of 5, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Electronic design automation › logic synthesis circuit optimization	1	1995	Delay optimization of digital CMOS VLSI circuits by transistor reordering · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995
Integrated circuit design › digital circuit design CMOS circuit design	1	1995	Delay optimization of digital CMOS VLSI circuits by transistor reordering · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995
Electronic design automation › physical design › timing optimization delay optimization	1	1995	Delay optimization of digital CMOS VLSI circuits by transistor reordering · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995
Electronic design automation › physical design › timing optimization propagation delay optimization	1	1995	Delay optimization of digital CMOS VLSI circuits by transistor reordering · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995
Electronic design automation › physical design › cell layout transistor reordering	1	1995	Delay optimization of digital CMOS VLSI circuits by transistor reordering · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995

Methods — techniques the papers use, named apart from their topics

transistor sizing · 0.0transistor reordering · 0.0

Year	Publication	Venue	Position
1995	Delay optimization of digital CMOS VLSI circuits by transistor reordering abstract In this paper the effects of transistor reordering on the delay of CMOS digital circuits are investigated, and an efficient method which uses transistor reordering for the delay optimization of CMOS circuits is presented. The proposed technique achieves significant reduction in propagation delays with little effect on layout area and power dissipation. The technique can be coupled with transistor sizing to achieve the desired improvement in circuit delay. Experimental results for benchmark circuits are given in 2.0, 1.2, and 0.8 /spl mu/m CMOS technologies. The average improvement in delay for the 20 benchmarks used in this paper is 9.1%.> Bradley S. Carlson, Suh-Juch Lee	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2