This work presents a CMOS-compatible, energy-efficient, and trainable neuromorphic architecture employing LIF neurons, validated through mathematical analysis of the membrane potential dynamics. It is implemented in a modular$64\times 36$crossbar array for temporal sequential detection of 36 alphanumeric patterns, each represented by an$8\times 8$pixel input. A novel spike mismatch detection cell, implemented in UMC 65-nm CMOS technology, enables pixel-wise comparison using two mutually inhibiting LIF neurons and an output neuron that spikes only on mismatches. Column-wise mismatch spikes encode similarity, while a simplified analog winner-take-all (WTA) logic identifies the best-matching pattern and is capable of identifying both positional and density variations. Each modular cell occupies an area of approximately$608~\mu \text {m}^{2}$, with an average power of$25.82~\mu $W per column and energy of 64.55 pJ per inference (0–$2.5~\mu $s), and Monte Carlo simulations showed process/temperature robustness. An accuracy of >95% was achieved under 2–3 pixel perturbations. Real-time validation with fixed alphanumeric inputs confirmed reliable operation at up to 1 MHz with$0.25~\mu $s setup time. A hardware prototype for the proposed block using discrete ICs (SN7404, CD4007) further demonstrated precise spike generation and effective inhibition.

Object detection and recognition are crucial for autonomous vehicles, surveillance systems, and human-computer interaction. We present a new fully complementary metal-oxide semiconductor (CMOS) circuit-based system for object detection and recognition using a Spiking Neural Network (SNN). Our holistic CMOS circuit integrates neuromorphic elements, including a leaky integrate-and-fire (LIF) neuron model, spike time-dependent plasticity (STDP) memristor synapse, and basic analog and digital building blocks. The learning mechanism is manifested by a completely different approach based on an array of XOR gates to recognize six different objects with 256 × 6 size crossbar arrays. This is the first-ever recognition mechanism of its kind. We also perform handwritten digit recognition using a 64 × 4 size array using grayscale conversion. The proposed system’s robustness is validated through process corner simulations, noise analysis, and temperature analysis. We also show the accuracy of our design for the digit recognition task using a confusion matrix plot, and the accuracy turns out to be 82.5 %. Our pioneering approach using a CMOS memristor-emulator STDP crosspoint array-based architecture achieves minimal energy consumption per neuron block, which amounts to ≈ 2.59 pJ per neuron block and an overall energy budget of 663.66 pJ for the entire system considering the object recognition task.

We present a new CMOS circuit and its successful fabrication of an operational transconductance amplifier (OTA)-CMOS inverter-based memristor emulator and investigate its switching behavior from 5 MHz to 50 MHz. It could be considered the first memristor emulator based on a current mode circuit and an inverter. Primarily, the transconductance of the inverter stage transforms the bias-voltage-dependent transconductance of the OTA into an overall flux-dependent memductance of the memristor. We also demonstrate how performance measures such as frequency response, noise, post-layout simulation, and process corners impact the memristive behavior of the design. The power consumption of the proposed memristor emulator is 2.25 mW. The aforementioned power figure is based on a 1.8 V power supply and calculated on a UMC 180-nm CMOS technology node. Further, using this memristor emulator, we implement a CMOS circuit for spiking signal generation called the Memristive Integrate-and-Fire (MIF) neuron circuit that mimics a biological neuron. As far as we know, a spiking signal generation using a memristor emulator remains unreported. Later on, we went on to realize a MIF neuron based object detection application to bring out the practical significance of the MIF neuron circuit. We have fabricated a chip of the proposed memristor emulator design with the die size of L=$1499.96~\mu \text{m}$, W=$1499.96~\mu \text{m}$, and included its fabrication result to validate the theoretical derivations in the work. At last, we perform an experimental realization of a chaos circuit application with the help of the fabricated chip.

Balanced ternary digital logic circuits based on memristors and MOSFET devices are introduced. First, balanced ternary minimum gate TMIN, maximum gate TMAX and ternary inverters are designed and verified by simulation. Next, logic circuits such as ternary encoders, decoders and multiplexers are designed using these three basic gates. For further validation, a ternary 3–1 encoder was hardware-implemented successfully using in-house fabricated memristors and MOS transistors. Two different design approaches, namely the decoder-based method and the multiplexer-based method are introduced and applied to realize combinational logic circuits such as balanced ternary half-adder, multiplier, and numerical comparator. We simulate the circuits using 50nm CMOS technology parameters and BSIM models and present comparisons and analyses of the two design methods in view of the power consumption and component device counts, which can guide subsequent research and development of integrated multi-valued logic circuits. The decoder-based method has advantages both in terms of component numbers and power consumption, but the multiplexer-based method has the advantages of being based on a simple operating principle and ease of implementation.

We present a fully memristive spiking neural network (MSNN) consisting of novel memristive neurons trained using the backpropagation through time (BPTT) learning rule. Gradient descent is applied directly to the memristive integrate-and-fire (MIF) neuron designed using analog SPICE circuit models, which generates distinct depolarization, hyperpolarization, and repolarization voltage waveforms. Synaptic weights are trained by BPTT using the membrane potential of the MIF neuron model and can be processed on memristive crossbars. The natural spiking dynamics of the MIF neuron model are fully differentiable, eliminating the need for gradient approximations that are prevalent in the spiking neural network literature. Despite the added complexity of training directly on SPICE circuit models, we achieve 97.58% accuracy on the MNIST test set and 75.26% on the Fashion-MNIST test set, which is considerably high among all fully MSNNs with small-scale neural networks.

We present a fully memristive spiking neural network (MSNN) consisting of physically-realizable memristive neurons and memristive synapses to implement an unsupervised Spike Timing Dependent Plasticity (STDP) learning rule. The system is fully memristive in that both neuronal and synaptic dynamics can be realized by using memristors. The neuron is implemented using the SPICE-level memristive integrate-and-fire (MIF) model, which consists of a minimal number of circuit elements necessary to achieve distinct depolarization, hyperpolarization, and repolarization voltage waveforms. The proposed MSNN uniquely implements STDP learning by using cumulative weight changes in memristive synapses from the voltage waveform changes across the synapses, which arise from the presynaptic and postsynaptic spiking voltage signals during the training process. Two types of MSNN architectures are investigated: 1) a biologically plausible memory retrieval system, and 2) a multi-class classification system. Our circuit simulation results verify the MSNN’s unsupervised learning efficacy by replicating biological memory retrieval mechanisms, and achieving 97.5% accuracy in a 4-pattern recognition problem in a large scale discriminative MSNN.

This paper presents a series of multi-stage hybrid memristor-CMOS ternary combinational logic stages that are optimized for reducing silicon area occupation. Prior demonstrations of memristive logic are typically constrained to single-stage logic due to the variety of challenges that affect device performance. Noise accumulation across subsequent stages can be amortized by integrating ternary logic gates, thus enabling higher density data transmission, where more complex computation can take place within a smaller number of stages when compared to single-bit computation. We present the design of a ternary half adder, a ternary full adder, a ternary multiplier, and a ternary magnitude comparator. These designs are simulated in SPICE using the broadly accessible Knowm memristor model, and we perform experimental validation of individual stages using an in-house fabricated Si-doped HfOxmemristor which exhibits low cycle-to-cycle variation, and thus contributes to robust long-term performance. We ultimately show an improvement in data density in each logic block of between$5.2\times - 17.3\times $, which also accounts for intermediate voltage buffering to alleviate the memristive loading problem.

The search for a compatible application of memristor-CMOS logic gates has remained elusive, as the data density benefits are offset by slow switching speeds and resistive dissipation. Active microdisplays typically prioritize pixel density (and therefore resolution) over that of speed, where the most widely used refresh rates fall between 25–240 Hz. Therefore, memristor-CMOS logic is a promising fit for peripheral I/O logic in active matrix displays. In this paper, we design and implement a ternary 1–3 line decoder and a ternary 2–9 line decoder which are used to program a seven segment LED display. SPICE simulations are conducted in a 50-nm process, and the decoders are synthesized on an Altera Cyclone IV field-programmable gate array (FPGA) development board which implements a ternary memristor model designed in Quartus II. Our approach to logic synthesis demonstrates a potential way forward for simulating large-scale memristor-CMOS circuits without embedded RRAM for functional verification, and our SPICE results show an improvement in data density of a variety of decoders by a factor between 3.6-8.5. While the switching speed of memristors are one of several bottlenecks to using them in combinational logic, the comparatively slow refresh rates of typical microdisplays indicate this to be a tolerable trade-off, which promotes data density over speed.

Deep neural network inference accelerators are rapidly growing in importance as we turn to massively parallelized processing beyond GPUs and ASICs. The dominant operation in feedforward inference is the multiply-and-accumlate process, where each column in a crossbar generates the current response of a single neuron. As a result, memristor crossbar arrays parallelize inference and image processing tasks very efficiently. In this brief, we present a 3-D active memristor crossbar array 'CrossStack', which adopts stacked pairs of Al/TiO2/TiO2-x/Al devices with common middle electrodes. By designing CMOS-memristor hybrid cells used in the layout of the array, CrossStack can operate in one of two user-configurable modes as a reconfigurable inference engine: 1) expansion mode and 2) deep-net mode. In expansion mode, the resolution of the network is doubled by increasing the number of inputs for a given chip area, reducing IR drop by 22%. In deep-net mode, inference speed per-10-bit convolution is improved by 29% by simultaneously using one TiO2/TiO2-xlayer for read processes, and the other for write processes. We experimentally verify both modes on our 10 × 10 × 2 array.

We present and experimentally validate two minimal compact memristive models for spiking neuronal signal generation using commercially available low-cost components. The first neuron model is called the Memristive Integrate-and-Fire (MIF) model, for neuronal signaling with two voltage levels: the spike-peak, and the rest-potential. The second model MIF2 is also presented, which promotes local adaptation by accounting for a third refractory voltage level during hyperpolarization. We show both compact models are minimal in terms of the number of circuit elements and integration area. Using the MIF and MIF2 models, we postulate the design of a memristive solid-state brain with an estimation of its surface area and power consumption. Analytical projections show that a memristive solid-state brain could be realized within (i) the surface area of the median human brain, 2,400cm2, (ii) the same volume of the median human brain, and (iii) a total power budget of approximately 20 W using a 3.5 nm technology. Distinct from the past decade of memristive neuron literature, our benchmarks are attained using generic commercially available memristors that are reproducible using off-the-shelf components. We expect this work can promote more experimental demonstrations of memristive circuits that do not rely on prohibitively expensive fabrication processes.

This paper presents the first experimental demonstration of a ternary memristor-CMOS logic family. We systematically design, simulate and experimentally verify the primitive logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.

Existing computational models of the retina often compromise between the biophysical accuracy and a hardware-adaptable methodology of implementation. When compared to the current modes of vision restoration, algorithmic models often contain a greater correlation between stimuli and the affected neural network, but lack physical hardware practicality. Thus, if the present processing methods are adapted to complement very-large-scale circuit design techniques, it is anticipated that it will engender a more feasible approach to the physical construction of the artificial retina. The computational model presented in this research serves to provide a fast and accurate predictive model of the retina, a deeper understanding of neural responses to visual stimulation, and an architecture that can realistically be transformed into a hardware device. Traditionally, implicit (or semi-implicit) ordinary differential equations (OES) have been used for optimal speed and accuracy. We present a novel approach that requires the effective integration of different dynamical time scales within a unified framework of neural responses, where the rod, cone, amacrine, bipolar, and ganglion cells correspond to the implemented pathways. Furthermore, we show that adopting numerical integration can both accelerate retinal pathway simulations by more than 50% when compared with traditional ODE solvers in some cases, and prove to be a more realizable solution for the hardware implementation of predictive retinal models.

Biological neural systems use self- reconfigurable and self-learning primitive elements (synapses) to extract relevant information from complex and noisy environments, to detect specific spatio-temporal patterns in the data of interest and to compute and simultaneously store some significant features. All these desirable attributes may be realized by using two-terminal elements, memristors (memory resistors), which most closely resemble biological synapses. This article is organized according to the rule of the ISCAS2013 special session having the same title. We present a short summary of the state-of-the-art of memristor theory and Hodgkin-Huxley neural model. In addition, we briefly introduce a comprehensive nonlinear circuit-theoretic foundation for a novel circuit implementation of the Hodgkin-Huxley neural model with memristors.

Large-capacity content addressable memory (CAM) is a key element in a wide variety of applications. The inevitable complexities of scaling MOS transistors introduce a major challenge in the realization of such systems. Convergence of disparate technologies, which are compatible with CMOS processing, may allow extension of Moore's Law for a few more years. This paper provides a new approach towards the design and modeling of Memory resistor (Memristor)-based CAM (MCAM) using a combination of memristor MOS devices to form the core of a memory/compare logic cell that forms the building block of the CAM architecture. The non-volatile characteristic and the nanoscale geometry together with compatibility of the memristor with CMOS processing technology increases the packing density, provides for new approaches towards power management through disabling CAM blocks without loss of stored data, reduces power dissipation, and has scope for speed improvement as the technology matures.