This work demonstrates the benefit of spatial selectivity that a 4-element passive-beamforming continuous-time ADC can offer for the extreme dynamic range requirements in automotive radar. The beamforming-ADC is implemented in 40nm CMOS by R2R-based vector modulators as feed-in coefficients in combination with low-power implementations of a 4th-order inverter-based loop-filter, 4-bit asynchronous SAR-based quantizer and 4-bit current-steering feedback DACs. This work obtains >30dB of interferer suppression when deep notches are formed to obtain an effective spatial blocker dynamic range of 73.1dB. With notch-smoothing, the versatility to reduce the peak-to-notch-depth to 8dB for channel equalization is demonstrated. The beamforming-ADC consumes 7.3mW.

This paper proposes a self-corrected In- phase/Quadrature-phase (I/Q) digital Cartesian modulator. The modulator is comprised of double balanced Gilbert cells to mitigate code dependent input and output impedances. Transistor-level simulations in 28 nm bulk CMOS demonstrate a static error vector magnitude (EVM) of -35 dB at 79 GHz carrier while providing 9.5 dBm peak output power with ~19% drain efficiency. Transistor level analysis shows that the linearity is limited by the transconductance (gm) I and Q input code dependency. To address this dependency a self-contained 2-dimensional correction technique is proposed.The proposed correction method improves the EVM from -35 dB to -42.5 dB without compromising the output power, power efficiency and occupied silicon area. The proposed solution enables linear and power efficient transmitters (TXs) for mm-Wave applications.

This paper analyzes the error mechanisms that limit the dynamic range (DR) of wide-bandwidth, low-OSR continuous-time (CT) multi-stage noise-shaping (MASH) ΔΣM and proposes a tool, the Signal Leakage Function (SLF), to optimize the architecture, and hence improving DR. The SLF provides new insights on finding the key parameters which influence the inter-stage signal leakage and thus the inter-stage gain (IG). These insights would lead not only to increasing the overall dynamic range in a very power-efficient way, but also decreasing the performance sensitivity to mismatches and other variations.

This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.

This paper presents a 2 GHz 4-bit asynchronous successive approximation register (SAR) quantizer to enable an ultra-wideband continuous-time (CT) sigma-delta modulator (SDM). Low latency is required for the stability of the SDM. The excess-loop-delay compensation (ELDC) is embedded in the SAR quantizer by adding an extra switched-capacitor DAC segment with two separate reference voltages. To achieve high speed, a gm-boosted StrongARM latch and the monotonic switching scheme are used. This paper presents the transistor-level circuit implementation and the complete verification of the CT SDM. Simulation results show the power consumption of this SAR-based quantizer including ELDC is 0.98 mW, leading to a very competitive Figure-of-Merit of 30.6 fJ/conv.-step.

This paper proposes both system-level and circuit-level solutions of a current-mode multi-path excess loop delay (ELD) compensation technique for continuous-time (CT) ΣΔ ADCs with multi-bit quantization and several GHz sampling rate. Thanks to the proposed solutions, the amplifier of the loop filter is not in the fast feedback (FB) loop; the delay of the pre-amplifier of the comparator is removed; and the effective regeneration time of the comparator latch is maximized. The proposed novelties enable CT ΣΔ ADCs with wide signal bandwidth and improved power efficiency. Extensive transistor-level simulations demonstrate their effectiveness and robustness. This work validates the proposed methods by transistor level design and simulations of an 8.4 GHz MASH ΣΔ ADC achieving an SNDR of 71 dB in a signal band of 600 MHz. This shows that our proposed solutions enable power-efficient multi-GHz ΣΔ ADC applications.

This paper proposes a simple digital automatic calibration method for wide-band continuous-time (CT) MASH ΣΔ ADCs. The main contribution of this method is the calibration of the errors due to the limited DC gain and 2nd pole of the loop filter integrators. The digital noise cancellation filters are calibrated by successive estimation of the DC gains and the 2nd pole, and updating the coefficients of the FIR filters. Extensive system-level and transistor-level simulations demonstrate the effectiveness and robustness of the proposed method. For an exemplary MASH ΣΔ ADC with BW of 600 MHz and SQNR of 75 dB, it can relax the DC gain requirement by 15 dB, and the 2nd pole requirement by three time, making it an enabling technique for power-efficient GHz-range ΣΔ ADC applications.

This paper presents a 3.5 GS/s 6-bit current-steering digital-to-analog converter (DAC) with auxiliary circuitry to assist testing in a 1 V digital 28-nm CMOS process. The DAC uses only thin-oxide transistors and occupies 0.035 mm2, making it suitable to embedding in VLSI systems, e.g., field-programmable gate array (FPGA). To cope with the IC process variability, a unit element approach is generally employed. The three most significant bit (MSBs) are implemented as seven unary D/A cells and the three least significant bits (LSBs) as three binary D/A cells, using appropriately reduced number of unit elements. Furthermore, all digital gates only make use of two basic unit blocks: a buffer and a multiplexer. For testing, a memory block of 5 kb is placed on-chip, which is externally loaded in a serial way but internally read in an 8× time-interleaved way. The memory is organized around 48 clocked 104-bit shift-registers. It keeps the resulting switching disturbances signal-independent and hence avoids inducing output nonlinearity errors, even when a common power supply is shared with the DAC. This novelty allows reliable testing of the DAC core, while avoiding performance limitation risks of handling high-speed off-chip data streams. The DAC Spurious Free Dyanmic Range >40 dB bandwidth is 0.8 GHz, while the IM3 <;-40 dB bandwidth exceeds 1.3 GHz. The DAC consumes 53 mW of power and the design-for-test scheme -80 mW.

This brief presents a 7-GS/s 6-bit current-steering digital-to-analog converter (DAC) in 28-nm CMOS for VLSI System On Chip I/O embedding with an on-chip memory and clock generation circuits for wafer-sort testing. It demonstrates how Spurious Free Dynamic Range >50 dB can be maintained up to 1 GHz, while keeping the DAC footprint small -0.035 mm2. Several linearization techniques, such as current source cascodes with local biasing, thick-oxide output cascodes, bleeding currents, and 50% level of segmentation are validated for the first time at such very high frequencies. Testing is facilitated by means of integrating a digital front-end design-for-test scheme in 0.048 mm2. It uses a 5-kb 8X TI data memory, based on circular shift registers to avoid signal-dependent disturbances. An integrated 7-GHz Current Mode Logic ring oscillator-type clock generator and a serial data interface enable simple testing of the DAC at reduced cost.

In current steering Mixing-DACs with local mixing, timing errors between the current cells is a major concern. This paper considers two types of random timing errors: delay and duty-cycle. Analysis shows that the Mixing-DAC is sensitive to delay errors, but much less sensitive to duty-cycle errors. For the required high spectral purity of future 4GHz multicarrier GSM (SFDRRBW=85dBc), the delay spread σ(delay) should be <;36fs. Therefore, only mixing in the output stage with a single LO driver can achieve the desired linearity. The presented analysis shows that the timing of the binary cells in the segmented converter is very important, especially in a back-off scenario. Simulations confirm that accurate capacitance scaling at the high-frequency nodes of the binary current cells is crucial. A new, back-off aware segmentation trade-off is proposed, which shows the impact of the SFDRRBW and backoff requirements on the segmentation choice. The proposed methods result in an optimal Mixing-DAC architecture, implemented in 65nm CMOS, with a simulated performance of SFDRRBW=86dBc at 4GHz output frequency and -16dBFS/tone output power (10dB back-off).

In an RF transmitter, the function of the mixer and the DAC can be combined in a single block: the Mixing-DAC. For the generation of multicarrier GSM signals in a basestation, high dynamic linearity is required, i.e. SFDR>;85dBc, at high output signal frequency, i.e. fout≈ 4GHz. This represents a challenge which cannot be addressed efficiently by current available hardware or state-of-the-art published solutions. Mixing locality indicates if the mixing operation is executed locally in each DAC unit cell or globally on the combined DAC output signal. The mixing locality is identified as one of the most important aspects of the Mixing-DAC architecture with respect to linearity. Simulations of a current steering Mixing-DAC show that local mixing with a local output cascode can result in the highest linearity, i.e. IMD3out=4GHz.

This paper presents a new foreground DAC calibration method that is insensitive to temperature fluctuations and on-chip disturbances. In the proposed current cell, the same number of unit transistors is always used, guaranteeing matched response for all current cells. These transistors are divided in two groups: a fixed group and a configurable group. The unit transistors in the configurable group can be interchanged with additional redundant unit transistors, such that the mismatch errors of the configurable group compensate the mismatch errors of the fixed group. Together they generate the needed output current. Thus all current cells feature matched temperature coefficients and dynamic response. For an exemplary 6+6bits segmented current steering DAC, the expected 99% yield INL improves with almost 3 bits while using only 30% additional unit transistors.

This paper presents a DAC architecture built on parallel current-steering sub-DAC entities. Two main novelties are explored: flexibility and smartness. Firstly, a number of available operating modes (op-modes) can set the overall DAC performance and functionality. These op-modes transfer some of the important design trade-offs to the end-user and constitute the DAC flexibility. The main examples include: resolution-power-number of DACs, static-dynamic performance, etc. Secondly, specific signal processing techniques become possible. The main examples of such techniques include: full self-calibration, cancellation of harmonic distortion (HD) components, and linearity improvement through redundancy. This paper concentrates on a method to suppress undesired HD components through DA processing of phase shifted replicas of the main input signal. The presented theoretical concepts are realized in a 14-bit DAC built from 4 parallel 12-bit sub-DACs. Transistor simulations and a layout design are also presented. The demonstrated flexibility characteristics of the new DAC architecture make the discussed concepts particularly suitable for FPGA integration.

This paper describes an architecture for binary-to-thermometer decoders used in segmented D/A converters. To improve basic converter characteristics, the architecture features redundant output thermometer code. The main concept offers two modes of operation. Each mode generates a different thermometer output, i.e. a different switching sequence for the DAC MSB thermometer analog elements. This results in two different transfer characteristics of the whole DAC for the same mismatch errors of its elements. After on-chip or off-chip measurements, the more linear transfer characteristic can be selected. In this way, chip yield is improved and the design requirements can be relaxed. Ultimately, the advantages introduced by the proposed decoder lead to cheaper and smaller D/A converters.