Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from EDBT 2026 / reviewers in the wild / expert

Peter Kamarchik

dblp:57/284 · DBLP profile ↗
← Back
2ranked-venue papers
0as first author
0since 2021 · last 2000
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 44% Interconnection networks and networks-on-chip · 44% Energy-efficient computing · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs › FPGA architecture
island-style architecture		 0.012000
Scalable interconnect and power distribution for island-style FPGAs (poster abstract) · FPGA 2000
Interconnection networks and networks-on-chip › interconnect architecture
scalable interconnect		 0.012000
Scalable interconnect and power distribution for island-style FPGAs (poster abstract) · FPGA 2000
Energy-efficient computing › power delivery
power distribution		 0.012000
Scalable interconnect and power distribution for island-style FPGAs (poster abstract) · FPGA 2000
YearPublicationVenuePosition
2000 Tunable Fault Tolerance for Runtime Reconfigurable Architectures
abstract
Fault tolerance is becoming an increasingly important issue, especially in mission-critical applications where data integrity is a paramount concern. Performance, however, remains a large driving force in the market place. Runtime reconfigurable hardware architectures have the power to balance fault tolerance with performance, allowing the amount of fault tolerance to be tuned at run-time. This paper describes a new built-in self-test designed to run on, and take advantage of, runtime reconfigurable architectures using the PipeRench architecture as a model. In addition, this paper introduces a new metric by which a user can set the desired fault tolerance of a runtime reconfigurable device.
Steven K. Sinha, Peter Kamarchik, Seth Copen Goldstein
 FCCM2
2000 Scalable interconnect and power distribution for island-style FPGAs (poster abstract)
abstract
No abstract available.
Herman Schmit, David Whelihan, Peter Kamarchik, Frank Gennari
 FPGA3