EDBT 2026 Demo / reviewers in the wild / expert
Clark Mobarry
dblp:57/2907
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1995
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 91% Performance modeling and evaluation · 9% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache coherence |
0.0 | 1 | 1995 | A Performance Evaluation of the Convex SPP-1000 Scalable Shared Memory Parallel Computer · SC 1995 |
Memory systems
non-uniform memory access |
0.0 | 1 | 1995 | A Performance Evaluation of the Convex SPP-1000 Scalable Shared Memory Parallel Computer · SC 1995 |
Memory systems › shared memory
scalable shared memory |
0.0 | 1 | 1995 | A Performance Evaluation of the Convex SPP-1000 Scalable Shared Memory Parallel Computer · SC 1995 |
Performance modeling and evaluation
benchmarking |
0.0 | 1 | 1995 | A Performance Evaluation of the Convex SPP-1000 Scalable Shared Memory Parallel Computer · SC 1995 |
Methods — techniques the papers use, named apart from their topics
synthetic benchmarks · 0.0application benchmarks · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1995 | A Performance Evaluation of the Convex SPP-1000 Scalable Shared Memory Parallel ComputerabstractThe Convex SPP-1000 is the first commercial implementation of a new generation of scalable shared memory parallel computers with full cache coherence. It employs a hierarchical structure of processing communication and memory name-space management resources to provide a scalable NUMA environment. Ensembles of 8 HPPA-RISC7100 microprocessorsemploy an internal cross-bar switch and directory based cache coherence scheme to provide a tightly coupled SMP.Up to 16 processing ensembles are interconnected by a 4 ring network incorporating a full hardware implementation of the SCI protocol for a full system configuration of 128 processors. This paper presents the findings of a set of empirical studies using both synthetic test codes and full applications for the Earth and space sciences to characterize the performance properties of this new architecture. It is shown that overhead and latencies of global primitive mechanisms, while low in absolute time, are significantly more costl... Thomas L. Sterling, Daniel Savarese, Peter MacNeice, Kevin Olson, Clark Mobarry, Bruce Fryxell, Phillip Merkey |
SC | 5 |