In this paper, we present two generators for the group of symmetries of the generic (m+1) -dimensional periodic Costas arrays over elementary abelian (\BBZp)mgroups: one that is defined by multiplication onmdimensions and the other by shear (addition) onmdimensions. Through exhaustive search, we observe that these two generators characterize the group of symmetries for the examples we were able to compute. Following the results, we conjecture that these generators characterize the group of symmetries of the generic (m+1) -dimensional periodic Costas arrays over elementary abelian (\BBZp)mgroups.

The achievement of effective implementations to multi-FPGA architectures is greatly dependent on the process of partitioning. Although several automated high-level partitioning (HLP) methods have been reported (Srinivasan, et al., 2001) most of them are designed to solve general partitioning problems, and tend to apply generic local optimization techniques that miss out on alternate formulations that become apparent only with knowledge of the algorithm's functionality. The algorithmic formulation of discrete signal transforms (DST) especially that of the DFT has been extensively studied. Automated computational algebra platforms for the algorithmic manipulation of fast transform algorithms have been proposed, as well as automated methods to optimize DST implementations to general purpose processor platforms (Puschel et al., 2001) However, these methods have yet to be successfully adapted to automated partitioning methodologies for dedicated distributed hardware platforms

This paper introduces a high-level partitioning methodology which uses formulation-level discrete signal transform properties to provide improved results for their partitioning to multi-FPGA architectures. We review the global optimization scheme, the various methodology processes, and explain how their designs were influenced by characteristics of the discrete signal transforms and the target architecture. To illustrate our methodology's solution quality, we present results of partitioning several FFT sizes to a Berkeley emulation engine 2 multi-FPGA module.

In this paper, we describe a method to independently audit a physical design to identify inefficiencies detrimental to high quality routing. The method provides an exhaustive review of netlist structures having many possible equivalent solutions, such as buffer trees, as well as other structures with flexibility of implementation. In addition, the method provides a means to quantify the inefficiency, in terms of routing length and the impact to routing congestion. Lastly, the method gives physical design engineers a framework to quickly identify causes of routing congestion and identify structures that can be acted upon to enhance routing.