Low-temperature (LT) conditions can potentially lead to lower power consumption and enhanced performance in circuit operations by reducing the transistor leakage current, increasing carrier mobility, reducing wear-out, and reducing interconnect resistance. We develop PROCEED-LT, a pathfinding framework to co-optimize devices and circuits over a wide performance range. Our results demonstrate that circuit operations at LT (−196 °C) reduce power compared to room temperature (RT, 85 °C) by$15\times $to over$23.8\times $depending on performance level. Alternatively, LT improves performance by$2.4\times $(high-power, high-performance)$- 7.0\times $(low-power, low-performance) at the same power point. These gains are further improved in low-activity circuits and when using multivoltage configurations. Meanwhile, we highlight the need for improvement in$V_{\text {th}}$variation to leverage benefits at cryogenic temperatures.

An 86.6-dB SFDR, 1-GS/s differential bootstrap sampler in a 0.18-um SiGe BiCMOS technology is presented. The performance is achieved using an amplitude-modulated bootstrap circuit. The results show 14-bit linearity over nearly 500-MHz bandwidth, while consuming less power compared to a conventional MOSFET switched-capacitor bootstrap circuit due to less parasitic capacitance and the use of high ftHBT.

A 25Gb/s PAM-4 receiver is presented with 4- tap adaptive DFE and sampling clock optimization. PAM-4 signaling suffers more from non-optimal sampling clock phase which degrades BER. By finding the point with the least pre-cursor ISI, the sampling clock can be recovered with optimal phase, which improves the BER by as much as 109through 12.5dB channel loss. A novel clocked amplifier is implemented as a slicer to reduce the loop delay and meet the timing constraints of the direct feedback. Fabricated in 55nm CMOS technology, the receiver occupies 0.27mm2and consumes 185mW at 25Gb/s with a power supply of 1.2V.

This paper presents a highly digital calibration technique suitable for high-speed digital-to-analog converters (DACs). The proposed calibration method does not require an adjustment of on-chip analog voltages and can therefore be a favorable method in a deeply scaled nanometer process. The calibration utilizes that adding several redundant unit current cells to predetermined weight groups can be achieved with low hardware overhead, and choosing the best subset out of multitude of combinations leads to accuracy improvement. This paper proposes a two-step coarse-fine algorithm to choose the best subset for weight groups and analyzes the design tradeoff between the amount of redundancy and the expected yield via numerical simulations. To verify the proposed calibration method, a prototype 9-bit current-steering DAC has been implemented in 90-nm CMOS technology. The calibration algorithm is implemented as software to expedite the experiment. The measured results show that static linearity performance improves by 10.8× when the proposed calibration technique is applied. When running the DAC at 5-GS/s sampling speed, similar performance improvement has been observed, achieving peak signal-to-noise-distortion ratio of 54 dB at low frequency and 8-bit linearity when generating sinusoid up to 1 GHz.

This paper presents a high-voltage output stage suitable for square-wave drive in nanometer-scale CMOS technology. The output stage relies on device stacking to extend output swings reliably beyond that of the technology's supply rating. Two assisted-charging transistors are required for every additional stacked device to maintain reliability during switching transitions. Doubly- and triply-stacked drive circuits are designed using 2.5V thick-oxide devices in 65nm CMOS technology. Simulation results show that the two drivers operate reliably at 5V and 7.5V outputs respectively.

This paper presents a calibration technique for mismatch-constrained digital-to-analog converters (DACs). The architecture is based on a fully flexible unit current cell assignment. The calibration is performed in a highly digital manner and does not require adjustment of on-chip analog voltages. The method significantly improves low-frequency linearity of the DAC with low hardware overhead and is ideally applicable to low-frequency calibration or dc-trimming DACs. This paper proposes multitude of algorithms that seek to assign the unit cells to minimize the residual error along with tradeoffs between achievable accuracy and calibration complexity in the algorithms. To validate the proposed calibration method, a prototype currentsteering DAC has been implemented in 90-nm/1.2 V CMOS technology. The implementation is highly regular, making it suitable for the restrictive design rules of deep sub micron process technologies. The experimental result shows that more than 3-b of linearity improvement is achieved by applying the proposed calibration technique, showing that substantial net area saving is possible in comparison with the brute-force sizing method.

Static noise margin is one of the key metrics to estimate the likelihood of failure of a 6T-static random-access memory (SRAM) cell. This paper proposes a technique to accurately estimate the stability of a conventional SRAM cell without modifying the cell structure. The main idea is to measure the specific cell's currents with variant supply levels via the bit lines. The measured currents are used to estimate the read stability and the write ability through a nonlinear regression. The R2(coefficient of determination) of the stability estimation is as high as 0.95 when applied to an arbitrary data set. As typical stability definitions require an access to the internal node of a 6T-SRAM cell, alternative measurable stability metrics for read and write are surveyed and modified to improve the correlation with the conventional stability definition. With this alternative stability and the cell currents, the conversion rules from currents to the stability can be found from the measurement data. Simulation results show that the estimation error sigma is as small as 2.44% and 3% for the read stability and write-ability estimation, respectively. Validity of the idea is verified by Monte Carlo simulations by using SRAM models in a 45-nm CMOS technology.

The design of a high-speed reconfigurable analog-to-digital converter in 65-nm CMOS is described. Accuracy requirements are met without compromising the high-speed performance by using trimming-based offset cancellation. The ADC can be configured to work as a 3-bit, a 4-bit, or a 5-bit ADC with maximum integral nonlinearity (INL) and differential nonlinearity (DNL) of 0.48LSB and 0.35LSB respectively. The ADC achieves a figure-of-merit of 0.46pJ/conv-step and the active area is 0.13 mm2.

The increase in power dissipation of high-performance computing systems has driven the need for advance cooling systems. Recently, localized spot cooling using embedded thermoelectric coolers (eTECs) and chip-level cooling using miniature-scale refrigeration system have been demonstrated for mitigating thermal and power problems in high-performance computing systems. Operating integrated circuit at a lower temperature can result in reduced electronic power, improved reliability, and potentially improved speed. However, total power dissipation must include both the electronic power and the cooling power to quantify overall system performance. This paper explores the amount of total power reduction using two different types of cooling system for electronic cooling, by using a model that incorporates both a real-world microprocessor and cooling systems. The analysis indicates that an optimal operating point depends on the parameters of electronics and cooling systems. Our results show that cooling the right element (the cache) using eTEC gives a modest 3% improvement but provides the benefit of full integration. On the other hand, chip-level cooling using our refrigeration system results in a total power savings of 25% over the nonrefrigerated design.

Power dissipation of analog and mixed-signal circuits has emerged as a critical design constraint in today's VLSI systems. This paper presents a multilevel design optimization approach for reducing the power dissipation of a pipelined analog-to-digital converter (ADC). At the circuit-level, device-types and supply-voltages are jointly optimized for the residue amplifier of a pipeline stage to minimize power. At the architecture-level, the nonlinearity contribution from stage gain error is optimally distributed to further minimize combined power dissipation. The optimizations take advantage of an analytical optimization method based on geometric programming for a quantitative tradeoff analysis. All of the proposed power optimizations are applied to the design of a two-way interleaved 8-bit 320 MS/s pipelined ADC in 90-nm CMOS technology. Measured performance from a prototype chip shows 7.30-bit of ENOB at Nyquist input frequency with DNL of -0.35/+0.45 LSB and INL of -0.72/+0.89 LSB, while dissipating 12.77 mW from 2.1 V/1.2 V supplies. The achieved conversion efficiency is 253fJ/conv-step.

This paper presents a new method for fitting a convex piecewise-linear function to a given set of data, which can serve as an empirical modeling framework for circuit optimization via geometric programming. The method iteratively solves a series of linear optimization problems to minimize the fitting error. To reduce the fitting error in each iteration, an extra plane is added in the region where the largest error occurs. For verification, we apply the method to create transistor-level models in 90-nm complementary metal-oxide-semiconductor technology. Numerical results indicate that the proposed method can generate process-dependent transistor-level models with reasonable modeling accuracy.

This paper describes a stochastic jitter model for analyzing the performance and bit error rate (BER) of digital timing recovery circuits. The model uses parallel interconnected Markov chains to simulate the behavior of the system in response to both random and deterministic jitter. Unlike conventional Markov-chain models that require the system to be stationary, the parallel-chain model approximates deterministic changes in conditions with transitions between sub-chains. To verify the accuracy of the model, an analysis was performed on a digital delay-locked loop, and the results compared to measured data. The resulting transition probabilities and BER predicted by the proposed model are more than three orders of magnitude more accurate than those predicted by a conventional Markov-chain model.

Modern processing technologies offer a number of types of devices such as high-VT, low-VT, thick-oxide, etc. in addition to the nominal transistor in order to meet system performance and functional needs. While designers have leveraged these devices for mixed-signal design, a design framework is needed to guide designers in selecting the best set of devices. The same framework can enable device manufacturers decide which new devices to include in the suite of device offerings. This paper presents a design methodology that can quickly guide a designer in selecting the best set of devices for a given application, specifications, and circuit structure. The equation-based optimization framework based on geometric programming (GP) extends upon previous efforts that optimize sizing, biasing, and supply voltages. The paper first shows that convex piecewise-linear function fitting can effectively model for optimization all the types of devices offered by a 90 nm CMOS technology. Additionally, we show the potential to model and include experimental devices such as a Schottky tunneling source MOSFET. Second, the paper applies the model to an example circuit, a track-and-hold amplifier. The optimization and subsequent simulation illustrate the importance and amount of benefit from applying device selection.

This paper presents a feasible study of fully-integrated switching voltage regulators for power-optimized systems-on-chip (SoCs). In order to evaluate the power efficiency across a number of design variables, a compact macro-model of a regulator is created and validated. A key focus of the study is on the characteristics of the active and passive devices that are needed in order to maximize the efficiency of an on-chip regulator. With the macro-model, geometric programming is used to find the optimal characteristics for a given set of constraints such as load condition, process technology, and area. The achievable efficiencies for various current loads and across a range of technologies from 0.35-mum to 90-nm CMOS process are analyzed. The power efficiency is found to be strongly dependent on the inductor technology and over 70% efficiency is possible with advanced inductor technologies.

With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is constrained by a complex set of specifications such as voltage levels, voltage noise, signal deterministic jitter, random jitter, slew rate, BER etc. These specifications lead to complex tradeoffs for both circuits and circuit architecture in order to minimize power. This paper presents a design framework that enables the analysis of tradeoffs in the design of an I/O transmitter. The design framework includes BER analysis with a channel model coupled with logic sizing optimization that is constrained by the desired signaling specification.