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Robert F. Cmelik

dblp:57/3263 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 3 · 3 first-authorSystems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Performance modeling and evaluation · 52% Parallel and multicore computing · 24% Processor architecture and microarchitecture · 21%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 12 heaviest of 12, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation › simulation › processor simulation
instruction set simulation
0.011994
Shade: A Fast Instruction-Set Simulator for Execution Profiling · SIGMETRICS 1994
Performance modeling and evaluation
simulation
0.011994
Shade: A Fast Instruction-Set Simulator for Execution Profiling · SIGMETRICS 1994
Processor architecture and microarchitecture
instruction set architecture
0.011991
An Analysis of SPARC and MIPS Instruction Set Utilization on the SPEC Benchmarks · ASPLOS 1991
Processor architecture and microarchitecture › instruction set architecture
RISC
0.011991
An Analysis of SPARC and MIPS Instruction Set Utilization on the SPEC Benchmarks · ASPLOS 1991
Performance modeling and evaluation
workload characterization
0.011991
An Analysis of SPARC and MIPS Instruction Set Utilization on the SPEC Benchmarks · ASPLOS 1991
Parallel and multicore computing › parallel computing
parallel programming languages
0.011989
Experience with Multiple Processor Versions of Concurrent C · IEEE Trans. Software Eng. 1989
Parallel and multicore computing
parallel programming models
0.011989
Experience with Multiple Processor Versions of Concurrent C · IEEE Trans. Software Eng. 1989
Parallel and multicore computing
parallel programming runtimes
0.011989
Experience with Multiple Processor Versions of Concurrent C · IEEE Trans. Software Eng. 1989
Performance modeling and evaluation
profiling
0.011994
Shade: A Fast Instruction-Set Simulator for Execution Profiling · SIGMETRICS 1994
Performance modeling and evaluation › tracing
trace generation
0.011994
Shade: A Fast Instruction-Set Simulator for Execution Profiling · SIGMETRICS 1994
Compilers and program optimization
code generation
0.011991
An Analysis of SPARC and MIPS Instruction Set Utilization on the SPEC Benchmarks · ASPLOS 1991
Distributed systems
distributed programming
0.011989
Experience with Multiple Processor Versions of Concurrent C · IEEE Trans. Software Eng. 1989

Methods — techniques the papers use, named apart from their topics

dynamic instruction counting · 0.0dynamic binary translation · 0.0code caching · 0.0shared memory programming · 0.0message passing · 0.0
YearPublicationVenuePosition
1994 Shade: A Fast Instruction-Set Simulator for Execution Profiling
abstract
Tracing tools are used widely to help analyze, design, and tune both hardware and software systems. This paper describes a tool called Shade which combines efficient instruction-set simulation with a flexible, extensible trace generation capability. Efficiency is achieved by dynamically compiling and caching code to simulate and trace the application program. The user may control the extent of tracing in a variety of ways; arbitrarily detailed application state information may be collected during the simulation, but tracing less translates directly into greater efficiency. Current Shade implementations run on SPARC systems and simulate the SPARC (Versions 8 and 9) and MIPS I instruction sets. This paper describes the capabilities, design, implementation, and performance of Shade, and discusses instruction set emulation in general.
Robert F. Cmelik, David Keppel
SIGMETRICS1
1991 An Analysis of SPARC and MIPS Instruction Set Utilization on the SPEC Benchmarks
abstract
Copyright 1991, Association for Computing Machinery, Inc. Reprinted by permission. This paper originally appeared in Proceedings of the Fourth International Conference on Architecture Support for Programming Languages and Operating Systems (ASPLOS), Santa Clara, California, April 8-11, 1991. The dynamic instruction counts on MIPS and SPARC are compared using the SPEC benchmarks. MIPS typically executes more user-level instructions than SPARC. This difference can be counted for by architectural differences, compiler differences, and library differences. The most significant differences are that SPARC's double-precision floating point load/store is an architectural advantage in the SPEC floating point benchmarks while MIPS's compare-and-branch instruction is an architectural advantage in the SPEC integer benchmarks. After the differences in the two architectures are isolated, it appears that although MIPS and SPARC each have strengths and weaknesses in their compilers and library routines, the combined effect of compilers and library routines does not give either MIPS or SPARC a clear advantage in these areas.
Robert F. Cmelik, Shing I. Kong, David R. Ditzel, Edmund J. Kelly
ASPLOS1
1989 Experience with Multiple Processor Versions of Concurrent C
abstract
Concurrent C, a superset of C providing parallel programming facilities, is considered. A uniprocessor version of Concurrent C was first implemented. After experience with this version, the Concurrent C implementation was extended to run on two types of multiple processor systems: a set of computers connected by a local area network (the distributed version) and a shared-memory multiprocessor (the multiprocessor version). Experience with implementing and using these versions of Concurrent C is described. Specifically, the language changes triggered by the multiple processor implementations, some sample programs, a comparison of the execution times on various systems, and the suitability of these multiple processor architectures are discussed.>
Robert F. Cmelik, Narain H. Gehani, William D. Roome
IEEE Trans. Software Eng.1