Wearable physiological monitoring systems increasingly require continuous, low-power sensing interfaces capable of seamless integration into flexible Internet of Things (IoT) platforms. Conventional architectures rely on analog-to-digital converter (ADC) based front-ends and rigid electronics, which elevate system power, increase design complexity, and limit textilelevel conformity. To address these restraints, this paper presents a self-driven, fully integrated resistance-to-frequency converter system for continuous, and low-power wearable physiological monitoring. The proposed architecture eliminates conventional analog-to-digital converters (ADCs) and high-gain amplification stages by directly converting resistive strain variations into a frequency-modulated signal. The system comprises a flexible carbon-PDMS-based flexible sensor, exhibiting a gauge factor of approximately 80. The fabricated resistive sensor is embedded in a Wheatstone bridge front-end, which drives a lowcomplexity BJT-based push-pull astable oscillator operating in the 1–3 kHz band with a sensitivity of 50 Hz/kΩ. The BJTbased oscillator leverages a hybrid RC–LC topology, where an integrated inductor (L1) enhances the quality factor from 5 to 15, reducing phase noise by over 15 dB and directly improving startup reliability and temperature stability. The overall system is realized on a flexible PCB with an integrated mini ATmega16U4 microcontroller for frequency counting and an nRF52840 Bluetooth module for wireless transmission. Experimental validation demonstrates robust tracking of respiratory and body movement patterns with sub-hertz resolution, mean absolute error below 0.8 breaths per minute, and motion repeatability error under 3%. The design achieves an ultra-low duty-cycled power consumption, with a time-averaged current of 75 μA, enabling extended time operation from a 90 mAh battery. Finally, the system is fully textile-integrated using hand-knitting technique, ensuring user conformity by retaining >98% of its baseline electrical performance after 20 gentle machine-wash cycles.

This experience report is part of an ongoing NSF-funded grant project involving an alliance of six California State University campuses, aimed at promoting Latinx student retention through community engagement in early computer science courses. The project focuses on integrating socially responsible computing (SRC) into the curriculum to transform computing culture and invite marginalized students to participate. At our campus, we integrated SRC concepts into the CS2 course on Data Structures and Algorithms. Initially, SRC concepts were introduced into assignments and projects, which showed promising results but highlighted challenges: the assignments and projects were instructor-created, leading to a gap between students and the concepts. Students passively received topics without proactive participation, resulting in a lack of perceived real-world impact.

As the complexity and diversity of international conflicts intensify, designing international conflict scenarios based on causal inference is of significant importance and value for national decision-makers to grasp the key points of conflicts and achieve a scientific and effective national policy response. The study designs international conflict scenarios in three stages: data processing, structural model construction, and real-world situation fitting. Taking the construction of the Russia-Ukraine conflict scenario as an example, the study takes topic mining and causal inference methods based on conflict description texts to design scientific scenarios and analyze them to obtain reasonable policy recommendations, demonstrating the rationality of the scenario design method. The study not only provides a method for analyzing international conflicts to support practical policy generation but also offers a framework for scenario design using quantitative methods, which has important implications for future research and practice in related fields such as international political situations and military conflicts.

Abstract Radio frequency identification (RFID) is widely applied due to its fast identification speed and non-contact detection. However, the identification process of RFID tags is susceptible to interference from other tags and environmental factors, resulting in inaccurate identification data. To overcome these problem, this paper proposes an improved sensing data cleaning scheme for object localization in edge computing environment. In tag level data cleaning, we use adaptive sliding window and further consider dynamic tags and read rate in continuous reading cycle to adjust the window size timely and appropriately. In the reader level data cleaning, we estimate the tag number based on Chebyshev’s inequality through Markov chain for cyclic control and optimize different time slot lengths to improve the recognition rate. We build an edge computing environment and combine the proposed tag-level cleaning method and reader-level cleaning method to form a comprehensive RFID data cleaning process. Comparative experimental results show that the RFID data cleaning method proposed in this paper can effectively reduce redundant and missing data and improve the accuracy of tag recognition.

A novel down-sampling filter named moving accumulative sign filter (MASF) is proposed for low-power down-sampling of large-scale binary and ternary data. Besides, the MASF has greatly circuit realization advantages than state-of-the-art cascaded-integrator-comb (CIC) filter, especially in the area of low-power design. The theory of MASF is proposed and introduced comprehensively, including the algorithm model, transfer function, and frequency response characteristics. The pipeline voting architecture is applied to the implementation of the MASF to improve the speed of data processing, which simplifies the circuit structure and reduce the power consumption. The MASF circuits of general application based on pipeline voting are designed for binary and ternary signals only using D flip-flop and logic gates. The area and power consumption of MASF are reduced by 86% and 88% compared with CIC filter under the same conditions on FPGA. What’s more, a hardware-friendly pooling algorithm named polar-pooling is proposed based on MASF for binary and ternary feature maps, which greatly reduces the time and space complexity of pooling. Compared with max-pooling and average-pooling, the processing time of polar-pooling is reduced by more than 75% for a$200\times 200$binary image. The two-stage MASF circuit for ternary signal processing is implemented at 40-nm CMOS process, compared with state-of-the-arts cascade-of-integrators filter which cascading two integrators, the normalized power consumption of proposed two-stage MASF circuit has 67% reduction and the area has 75% reduction.

Cyclic redundancy check (CRC) and Forward error correction (FEC) encoding are widely used in high-speed information transceiver systems such as PCIe, JESD204C and fiber-optic communications to detect or correct errors in data. Traditionally, the CRC and FEC encoding circuits in JESD204C are implemented independently of each other, which consumes a significant amount of hardware resources. Therefore, a high logic density CRC and FEC logic sharing (CFLS) encoding circuit for JESD204C controller is proposed in this paper, and the logic density of the encoding circuit is improved by sharing the registers and common encoding factor (CEF). Meanwhile, a straightforward critical path delay (CPD) calculation method was proposed to assess whether the data transmission delay satisfies the requirements of CFLS circuits. This method is derived in conjunction with the manipulation of the common factor matrix, thus reducing computational complexity. The CFLS encoding circuit proposed in this paper is verified with an FPGA platform, and the results show that the circuit can realize CRC and FEC function with a 21.96% reduction in hardware resources, compared to the traditional methods. The area of the JESD204C controller with CFLS encoding circuits is 0.09 mm2, by using a 40-nm CMOS process, and the power consumption is 24.66 mW according to the post-layout simulation.

This paper presents a high-precision bandgap voltage reference (BGR) with high-order temperature compensation. The compensation signal is generated by using both strong-inversion MOSFETs and Bipolar Junction transistors (BJTs), which cancels the high-order nonlinear term$T\ln (T)$in the BJT base-emitter voltage (VBE), and thus a low temperature coefficient (TC) over a wide temperature range is achieved. The proposed BGR circuit is fabricated in a 0.18-$\mu \text{m}$CMOS process with an active area of$0.256 m{m^{2}}$and a max power consumption of 1.35 mW. A minimum TC of 0.706${\mathrm{ppm}}/{}^ \circ C$from$- 25\,\,{}^ \circ C$to 125${}^ \circ C$is achieved after an 8-bit resistance trimming. The line sensitivity is 0.0146%/V operating from 3.2 V to 3.7 V. The BGR achieves a power supply rejection (PSR) of −63.4 dB and a noise spectrum density of$0.92 ~\mu \text{V}/\sqrt {Hz} $at 10 Hz.

This paper introduces a broadband linear driver used in B-PLC system. The driver consists of two identical current-feedback amplifiers to realize a fully differential topology. A cross-current injection method between the noninverting and the inverting channels is proposed to reduce the even-order harmonics caused by the circuit mismatch. In addition, in order to increase the stability of the GBW to the changing load and maximize the bandwidth, a output stage implemented by a unit gain closed-loop amplifier is proposed to stabilize the open-loop gain of the overall circuit, meanwhile improve the linearity deteriorated by the crossover distortion. The proposed linear driver is fabricated in a SOI CBJT process and it can provide a maximum drive current of 500 mA under a 12-V power supply. The measurement results show that this linear driver is capable of driving a load of$50~\Omega $while achieving a output swing of$16~{V_{pp}}$with a second-order harmonic distortion (HD2) of −72 dBm and a third-order harmonic distortion (HD3) of −55 dBm. The bandwidth can reach 120 MHz. A complete in-system measurement also has been passed and the results show that the proposed driver chip can well meet the need of the B-PLC system.

In an 8B/10B mode giga-bit-per-second serial data transactions, the de-serialized data is sent to a comma detection and word alignment (CDWA) module to identify the word boundaries, which is a prerequisite in the high-speed transceivers such as PCIe, USB and JESD204B/C. In order to ensure that the comma code (/K/-code) can be correctly detected. Ten 10-bit comma detector cells are adopted in a typical CDWA module, which require a complex circuitry and an enormous power consumption. To overcome these limitations, a low-area and low-power CDWA circuit for JESD204B/C transceiver chip in 8B/10B mode has been proposed in this paper. The bit width of the detector cells can be truncated from 10 to 6 under the condition, that CDWA module can detect a complete comma code correctly. On one hand, the proposed CDWA module is verified with a FPGA development platform with the reduction of the hardware resources and power consumption to 31.72% and 20.11% respectively as compared to the typical structure available. On the other hand, a 10-Gbps transceiver chip with the proposed CDWA module is fabricated with a 55-nm CMOS process and the word alignment function of the proposed module is proved by the measurement results. The area of this transceiver chip including 2× transmitting links and 2× receiving links is 2.89 mm2, and the power consumption is 467.8 mW, under a maximum data transmission rate of 10 Gbps.

The important role of angiogenesis in cancer development has driven many researchers to investigate the prospects of noninvasive cancer diagnosis based on the technology of contrast-enhanced ultrasound (CEUS) imaging. This paper presents a deep learning framework to detect prostate cancer in the sequential CEUS images. The proposed method uniformly extracts features from both the spatial and the temporal dimensions by performing three-dimensional convolution operations, which captures the dynamic information of the perfusion process encoded in multiple adjacent frames for prostate cancer detection. The deep learning models were trained and validated against expert delineations over the CEUS images recorded using two types of contrast agents, i.e., the anti-PSMA based agent targeted to prostate cancer cells and the non-targeted blank agent. Experiments showed that the deep learning method achieved over 91 percent specificity and 90 percent average accuracy over the targeted CEUS images for prostate cancer detection, which was superior ( ) than previously reported approaches and implementations.

Existing ridesharing services have focused on on-demand trip matching, which resembles traditional taxi dispatching. This may encourage more private vehicles on the road, which aggravate traffic congestions in peak hours rather than alleviating them. We propose CommuteShare, a novel ridesharing service for daily commuters that encourages long-term ridesharing among commuters with similar commuting patterns, to increase the traffic efficiency in peak hours. We first identify commuting private vehicles (CPVs) from traffic records and model their commuting patterns. We then design a dynamic model to formulate the intention level of a CPV driver to offer a ride based on the spatio-temporal convenience and dynamic traffic conditions. Based on the commuting patterns of the CPVs and the dynamic model of the CPV drivers, we propose a ridesharing algorithm to compute ridesharing matches among CPVs. We perform extensive experiments on three real-world cross-domain urban big datasets from a major city of China. Experimental results show that, using the proposed CommuteShare service, over 5,300 private vehicles can be reduced daily on average during morning peak hours, with a reduction of 7-minute average waiting time for the riders.

The 2009 influenza pandemic teaches us how fast the influenza virus could spread globally within a short period of time. To address the challenge of timely global influenza surveillance, this paper presents a spatial-temporal method that incorporates heterogeneous data collected from the Internet to detect influenza epidemics in real time. Specifically, the influenza morbidity data, the influenza-related Google query data and news data, and the international air transportation data are integrated in a multivariate hidden Markov model, which is designed to describe the intrinsic temporal-geographical correlation of influenza transmission for surveillance purpose. Respective models are built for 106 countries and regions in the world. Despite that the WHO morbidity data are not always available for most countries, the proposed method achieves 90.26 to 97.10 percent accuracy on average for real-time detection of global influenza epidemics during the period from January 2005 to December 2015. Moreover, experiment shows that, the proposed method could even predict an influenza epidemic before it occurs with 89.20 percent accuracy on average. Timely international surveillance results may help the authorities to prevent and control the influenza disease at the early stage of a global influenza pandemic.

Deep neural networks (NNs) are the state-of-the-art models for understanding the content of images and videos. However, implementing deep NNs in embedded systems is a challenging task, e.g., a typical deep belief network could exhaust gigabytes of memory and result in bandwidth and computational bottlenecks. To address this challenge, this paper presents an algorithm and hardware codesign for efficient deep neural computation. A hardware-oriented deep learning algorithm, named the deep adaptive network, is proposed to explore the sparsity of neural connections. By adaptively removing the majority of neural connections and robustly representing the reserved connections using binary integers, the proposed algorithm could save up to 99.9% memory utility and computational resources without undermining classification accuracy. An efficient sparse-mapping-memory-based hardware architecture is proposed to fully take advantage of the algorithmic optimization. Different from traditional Von Neumann architecture, the deep-adaptive network on chip (DANoC) brings communication and computation in close proximity to avoid power-hungry parameter transfers between on-board memory and on-chip computational units. Experiments over different image classification benchmarks show that the DANoC system achieves competitively high accuracy and efficiency comparing with the state-of-the-art approaches.

This letter presents a novel deep learning algorithm for feature extraction from the hyperspectral images. The proposed method takes advantage of the knowledge that the features of the spatial-spectral data naturally fall into an array of groups with respect to different spectral bands. Aiming to reduce the influence of redundant spectral bands adaptively using unlabeled hyperspectral data, we incorporate the group information in the training algorithm of the deep neural network via a regularized weight-decay process. Experiments over different benchmarks of hyperspectral images show that the proposed method provides competitive solution with the state-of-the-art approaches.

The Global Influenza Surveillance Network is crucial for monitoring epidemic risk in participating countries. However, at present, the network has notable gaps in the developing world, principally in Africa and Asia where laboratory capabilities are limited. Moreover, for the last few years, various influenza viruses have been continuously emerging in the resource-limited countries, making these surveillance gaps a more imminent challenge. We present a spatial-transmission model to estimate epidemic risks in the countries where only partial or even no surveillance data are available. Motivated by the observation that countries in the same influenza transmission zone divided by the World Health Organization had similar transmission patterns, we propose to estimate the influenza epidemic risk of an unmonitored country by incorporating the surveillance data reported by countries of the same transmission zone. Experiments show that the risk estimates are highly correlated with the actual influenza morbidity trends for African and Asian countries. The proposed method may provide the much-needed capability to detect, assess, and notify potential influenza epidemics to the developing world.

An improved recycling folded cascode operational transconductance amplifier with gain boosting and enhanced phase-margin is proposed. Among four variants of folded cascode amplifiers that have been implemented in TSMC 0.18μm CMOS process under same power and area constraints, the proposed amplifier achieves the lowest settling error of less than 0.5% compared to 1.1% settling error by Improved Recycling Folded Cascode (IRFC), 1.4% settling error by Recycling Folded Cascode (RFC) and 30% settling error by conventional Folded Cascode (FC) amplifier. This performance enhancement is attributed to 30dB increment in low-frequency gain and 7° improvement in the phase margin when compared with the second best performing Improved Recycling Folded Cascode amplifier.

A sigma delta (ΣΔ) ADC for sensing application is presented in this paper. Several techniques are adopted to implement a low power high dynamic range ADC. Firstly, a single-stage inverter replaces the commonly used differential amplifier, in order to reduce the static current. Secondly, the normal NMOS transistor in the inverter stage is replaced by a high threshold device. As a result, with the same transistor size and supply voltage, the gain of the inverter can be enhanced while the short circuit current can be reduced. Thirdly, the charge leakage due to the forward-based parasitic diode is eliminated by using a charge protection switch and rearranged reference scheme. The proposed ΣΔ ADC is implemented and fabricated using TSMC 0.18μm technology. The simulation result shows that for a 1.8V supply, 25MHz sampling frequency and 125 oversampling ratio, the power consumption is 63.7μW and 116μW, dynamic range is 80dB and 83dB, the ENOB is 11.5 and 11.7bit for a single-ended and a pseudo-differential configurations, respectively. The presented ADC scheme can be applied in a Full HD image sensor running at up to 50 frames/s.

In this paper, a smart temperature sensor working at a supply voltage as low as 0.9V over the full military temperature range is presented. Low voltage operation is achieved by biasing the front-end BJT pairs with different emitter currents for two different sensing ranges, from -55°C to 30°C and from 20°C to 125°C, respectively. A second-order inverter-based ΣΔADC with dynamic element matching (DEM) and input signal chopping to control the conversion error to within 0:2°C is used for digital readout. Front-end bias currents are selected during the design stage to minimize the induced sensing error. The proposed sensor is implemented using the TSMC 0.18μm 1P6M process. Simulation result shows that a +1°C=-0:1°C sensing error using one-point calibration can be achieved from -55°C to 125°C. At a sampling speed of 20 samples/s, the sensor consumes 3.4μA and 4.7μA in the low temperature range and the high temperature range, respectively.

In this paper, we present a 4T low-power linear output current-mediated CMOS APS imager, in which reset and read-out operations are carried-out simultaneously on two pixels of the same row. The proposed operating technique greatly simplifies the pixel architecture with only four transistors and two control signals required, while six transistors and four control lines are required by its current-mediated counterpart. The imager achieves fixed pattern noise (FPN) correction during pixel-readout and exhibits a power consumption which is independent of the imager array size, since only a single current source is solicited at any given time due to the array-level operating technique. A linearization circuit technique using the transistor's channel length modulation effect is employed enabling to double the linear range of the pixel's photon-to-output signal transfer function. Performance analysis and experimental results are presented for a 32 × 32 image sensor array prototype, fabricated using AMS 0.35-μm process. The pixel size is 6.5 × 6.5 μm2with 22% fill-factor. The chip total power consumption is less than 1 mW, at 50 frames/s with a 3.3 V power supply.

This paper presents an approach that enables heterogeneous robots to automatically form groups as needed to generate both strongly-cooperative and weakly-cooperative multi-robot task solutions in the same application. The fundamental contribution of this work is the layering of our low-level coalition formation algorithm for generating strongly-cooperative task solutions, with high-level, traditional task allocation methods for weakly-cooperative task solutions. At the low level, coalitions that generate strongly-cooperative multi-robot task solutions are formed using our ASyMTRe-D approach that maps environmental sensors and perceptual and motor schemas to the required flow of information in the robot team, automatically reconfiguring the connections of schemas within and across robots to form efficient solutions. At the high level, a traditional task allocation approach is used to enable individual robots and/or coalitions to compete for weakly-cooperative task assignments through task allocation. We introduce the site clearing task to motivate the work, and then formalize the problem. We then present the approach of layering ASyMTRe-D with task allocation. We validate the approach on a team of robots with the site clearing task. We believe the resulting approach is a flexible system that can handle a broad range of realistic multi-robot applications beyond what is possible using other existing approaches.

This paper presents a reasoning system that enables a group of heterogeneous robots to form coalitions to accomplish a multirobot task using tightly coupled sensor sharing. Our approach, which we call ASyMTRe, maps environmental sensors and perceptual and motor control schemas to the required flow of information through the multirobot system, automatically reconfiguring the connections of schemas within and across robots to synthesize valid and efficient multirobot behaviors for accomplishing a multirobot task. We present the centralized anytime ASyMTRe configuration algorithm, proving that the algorithm is correct, and formally addressing issues of completeness and optimality. We then present a distributed version of ASyMTRe, called ASyMTRe-D, which uses communication to enable distributed coalition formation. We validate the centralized approach by applying the ASyMTRe methodology to two application scenarios: multirobot transportation and multirobot box pushing. We then validate the ASyMTRe-D implementation in the multirobot transportation task, illustrating its fault-tolerance capabilities. The advantages of this new approach are that it: 1) enables robots to synthesize new task solutions using fundamentally different combinations of sensors and effectors for different coalition compositions and 2) provides a general mechanism for sharing sensory information across networked robots

This paper describes a methodology for automat ically synthesizing task solutions for heterogeneous multi-robot teams. In contrast to prior approaches that require a manual pre definition of how the robot team will accomplish its task (while perhaps automating who performs which task), our approach automates both the how and the who to generate task solution approaches that were not explicitly defined by the designer a priori. The advantages of this new approach are that it: (1) enables the robot team to synthesize new task solutions that use fundamentally different combinations of robot behaviors for different team compositions, and (2) provides a general mechanism for sharing sensory information across networked robots, so that more capable robots can assist less capable robots in accomplishing their objectives. Our approach, which we call ASyMTRe (Automated Synthesis of Multi-robot Task solutions through software Reconfiguration, pronounced “Asymmetry”), is based on mapping environmental, perceptual, and motor control schemas to the required flow of information through the multi-robot system, automatically reconfiguring the connections of schemas within and across robots to synthesize valid and efficient multi-robot behaviors for accomplishing the team objectives. We validate this approach by presenting the results of applying our methodology to two different teaming scenarios: altruistic cooperation involving multi-robot transportation, and coalescent cooperation involving multi-robot box pushing.

This paper presents a distributed reasoning system, called ASyMTRe-D, which enables a team of robots to form coalitions to accomplish a multi-robot task through tightly-coupled sensor sharing. The theoretical foundation of the negotiation protocol is ASyMTRe, an approach we developed previously to synthesize task solutions according to the task requirements and the team composition. The goal of the ASyMTRe approach is to increase the task solution capabilities of heterogeneous multi-robot teams by changing the fundamental abstraction from the typical "task" abstraction to a "schema" abstraction and automatically reconfigure the schemas to address the task at hand. The decision-making in this prior work was fully centralized; the current paper presents a distributed version of this approach based on the contract net protocol, which can achieve higher levels of robustness than the centralized version. The purpose here is not to improve the original protocol, but to apply it to our problem so that the autonomous task solution capabilities of robots can be achieved in a distributed manner. Simulation results are provided to validate the protocol with performance analysis. Finally, we compare ASyMTRe-D with the centralized ASyMTRe. Our future objective is to enable the human designer to specify the desired balance between solution quality and robustness, enabling the reasoning approach to invoke the appropriate level of information-sharing among robots to reach the specified solution characteristics.

This paper presents the design and results of autonomous behaviors for tightly-coupled cooperation in heterogeneous robot teams, specifically for the task of navigation assistance. These cooperative behaviors enable capable, sensor rich ("leader") robots to assist in the navigation of sensor-limited ("simple") robots that have no onboard capabilities for obstacle avoidance or localization, and only minimal capabilities for kin recognition. The simple robots must be dispersed throughout a known, indoor environment to serve as a sensor network. However, because of their navigation limitations, they are unable to autonomously disperse themselves or move to planned sensor deployment positions independently. To address this challenge, we present cooperative behaviors for heterogeneous robots that enable the successful deployment of sensor-limited robots by assistance from more capable leader robots. These heterogeneous cooperative behaviors are quite complex, and involve the combination of several behavior components, including vision-based marker detection, autonomous teleoperation, color marker following in robot chains, laser-based localization, map-based path planning, and ad hoc mobile networking. We present the results of the implementation and extensive testing of these behaviors for deployment in a rigorous test environment. To our knowledge, this is the most complex heterogeneous robot team cooperative task ever attempted on physical robots. We consider it a significant success to have achieved such a high degree of system effectiveness, given the complexity of the overall heterogeneous system.