Andrew W. Poon

dblp:57/3449 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
0since 2021 · last 2009
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 81% Parallel and multicore computing · 19%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip
optical interconnection networks
0.112009
Cascaded Microresonator-Based Matrix Switch for Silicon On-Chip Optical Interconnection · Proc. IEEE 2009
Parallel and multicore computing › many-core systems
many-core computing
0.012009
Cascaded Microresonator-Based Matrix Switch for Silicon On-Chip Optical Interconnection · Proc. IEEE 2009
Interconnection networks and networks-on-chip
optical network-on-chip
0.012009
Cascaded Microresonator-Based Matrix Switch for Silicon On-Chip Optical Interconnection · Proc. IEEE 2009

Methods — techniques the papers use, named apart from their topics

multimode interference · 0.1microring resonators · 0.1
YearPublicationVenuePosition
2009 Cascaded Microresonator-Based Matrix Switch for Silicon On-Chip Optical Interconnection
abstract
This paper reviews developments in cascaded microresonator-based matrix switches for silicon photonic interconnection networks in many-core computing applications. Specifically, we emphasize our recently proposed 5$\times$5 matrix switch comprising two-dimensionally cascaded microring resonator-based electrooptic switches coupled to a waveguide cross-grid on a silicon chip. The cross-grid adopts low-loss low-crosstalk multimode-interference-based waveguide crossings. Such a microresonator-based matrix switch offers nonblocking interconnections among multiple inputs and multiple outputs, with the key merits of i) a tens to hundreds of micrometers-scale footprint, ii) gigabit/second-scale data transmission, iii) nanosecond-speed circuit-switching, iv) 100-$ \mu{\hbox{W}}$-scale dc power consumption per link, and v) large-scale integration for networks-on-chips applications. We analyze in detail the microring resonator-based cross-grid switch design for high-data-rate signal transmission in the context of our proposed 5$\times$5 matrix switch. We also study the feasibility of large-scale integration of the matrix switch. We report proof-of-concept experiments of a single cross-grid switch element and a 2$\times$2 matrix switch, propose design guidelines, and discuss future engineering challenges.
Andrew W. Poon, Xianshu Luo, Hui Chen 0033
Proc. IEEE1