In this work, a novel signal processing approach for the efficient computation of the cross-correlation operator on low-complexity FPGAs is presented. Sets-Of-Real-Numbers (SORNs) arithmetic is exploited to build resource-efficient multipliers that are carefully injected into the hardware architecture. By this measure, a significant decrease of arithmetic hardware requirements is achieved. Especially, in the scope of low-complexity FPGAs, this depicts an enormous advantage, as these devices usually only have a few or even no specific arithmetic hardware accelerators, such as DSP blocks, at all. In order to smoothly integrate these special multipliers, additional conversion functions are needed to handle the number format transformation between SORNs and the fixed-point (FxD) data representation. For the evaluation, several cross-correlation-related hardware architectures with different number formats, data types, and multipliers are taken into account. Out of this, the proposed SORN-based implementation turns out to achieve extremely high performance regarding the resulting signal quality. In terms of the resource utilization, it clearly outperforms the traditional FxD-based architectures. Hence, SORN-based multipliers identify as a powerful extension for calculating the cross-correlation on low-complexity FPGAs.

SORN Arithmetic is a low-complexity and low-precision digital number format based on intervals that can be useful for preprocessing large datasets. Since the interval width of a SORN result is likely to grow with the number of operations, the concept of fused SORN operations is proposed. Functions with more than one operation are evaluated without intermediate quantization, reducing spurious interval growth (the “dependency problem”) and increasing the resulting precision. The presented evaluations for basic and complex fused functions show a reduction of the output interval widths of up to 53%. In addition, introducing fused SORN operations also leads to significant hardware reductions in area, power consumption and path delay. Compared to the non-fused designs, reductions of the Area-Power-Timing-product of up to 88% can be achieved.

Sets-Of-Real-Numbers (SORN) Arithmetic derives from the Unum type-II number format and provides high throughput and low complexity computations at the cost of a very rough resolution. This work presents a symbol detection unit for MIMO transmission with a BPSK modulation which consists of a SORN preprocessor applying an exhaustive search method and a fixed-point module processing the results from the SORN unit. Different SORN datatypes and hardware configurations are considered and evaluated throughout BER simulations and postsynthesis analyses.

In this paper different SORN (Sets Of Real Numbers) datatype configurations are analyzed for unum type-2-based arithmetic applied to symbol detection in a wireless MIMO communication system. Different SORN interval properties and MIMO-specific performance measures as well as the corresponding hardware architectures are evaluated in order to rate the suitability of the different configurations for the target application. The evaluation of the proposed datatypes indicates an improvement in the solution set reduction of up to 95.4 % and a hardware complexity reduction of 30.3 % comparing the proposed 17 bit configuration to the original unum type-2-based 16 bit SORNs.

This article provides an efficient hardware generator for high-performance sets-of-real-numbers (SORNs) arithmetic. Complex datapaths are automatically built in VHDL, comprising the generation of arithmetic operations and functions as well as all necessary interconnects. Various SORN datatypes can be easily set up enabling high adaptivity to different applications. For further performance improvements additional optimization and implementation techniques are considered as well. For evaluation, a SORN-based symbol detector for a multiantenna wireless communication scenario is generated that solves a system of linear equations. As SORN-based signal processing allows a quick but rough calculation of the system equations outcome, it can be exploited to reject possible input vectors that do not satisfy the general constraints of the signal detection task. Hence, this generally leads to a heavily reduced set of remaining solutions. Multiple hardware architectures with different SORN datatypes are generated and compared. Further, an analysis is performed considering the signal-to-noise ratio (SNR). Finally, logic synthesis is applied to selected designs and compared to references from the literature highlighting this article to be highly hardware-efficient and suitable for application-specific signal processing.

The Blockchain technology has become one of the most groundbreaking discoveries of the last decade, encompassing a secure and distributed exchange of digital resources. By now, a large variety of applications and topics have been identified which have proven its feasibility. In this paper we discuss the deployment of Blockchains to manage concurrent industrial wireless premises networks. We propose a simple example of a Smart Contract protocol for distributed resource allocation, forcing the participants to reach an agreement on the wireless channel usage. A simple simulation model is set up highlighting Blockchain-based consensus findings as a promising approach for autonomous resource allocation within this application.

Resilient systems for future application as the Internet of Things (IoT), aerospace or automotive must satisfy demanding specifications over a 10-years lifespan. Thus, time-dependent degradation must be considered in early design stages. To ensure a realistic estimation of degradation impact a whole matrix decomposition algorithm is implemented in a 65nm CMOS technology with different multi threshold voltage standard cells, for a required low-power design. We present an assessment method based on stochastic mission profiles saving at least 10% area and power compared to common methods.

In this paper an on-line monitoring method for the threshold voltage of MOSFETs is presented. A state space model of the device under test is pre-fitted and used within a particle filter algorithm. The method is capable of extracting the threshold voltage in arbitrary mission or stress conditions. Thus, for reliability assessments the stress does not have to be relieved in order to measure a shift of the threshold voltage. Moreover, the monitoring is able to cancel out certain environmental influences such as temperature and supply voltage fluctuations which is a major improvement for any reliability assessment. The method is evaluated with TCAD (FDSOI Transistor) and SPICE (CMOS Transistor) simulations.

The bottleneck of recording multiple parallel channels with resource limited sensor circuits is the achievable data rate. Compressed Sensing (CS) is employed as a means of compressing the recorded data with minimally added hardware overhead. When recording multiple channels using CS one can choose to implement CS for each channel separately or using a multi channel approach to compress all signals at once. This paper presents an empirical study of these two options in terms of achievable reconstruction performance depending on the number of channels and it also presents possible circuit implementations based on successive approximation register digital to analog converter (SAR ADC). The multi channel approach requires a certain minimum number of input channels to be feasible. Exceeding this minimum will increase the performance beyond the limits of the single channel implementation.

Massive MIMO systems have become more popular in wireless communications due to their improved spectral efficiency compared to existing small-scale MIMO systems. However, current estimation methodes take too long for larger numbers of antennas. In this paper, a near-optimal iterative linear signal detection for massive MIMO is introduced exploiting the random projection method to approximate the channel matrix in a significantly lower dimensional space. This is then used as a preconditioner in the conjugate gradient least squares algorithm to enhance the convergence rate. For evaluation, different scenarios of spatial correlation in a massive MIMO system are considered. In contrast to other low-complexity signal detectors, our approach achieves excellent results in terms of robustness and determined latency.

The functionality of modern integrated circuits is affected by numerous non-ideal effects. Especially during the design of analog circuit components, much effort is invested in compensating these effects by various methods. In this work, an alternative approach is presented, which is based on digital calibration techniques and used in a sensor interface circuit. A suitable test signal is interleaved with the sensor signal, whereby the interface is permanently monitored. Static and dynamic errors are detected in this way without interrupting normal sensor activities. Afterwards, these errors are determined and corrected in the digital domain by adaptive filters. Hereby, an on-line error correction is realized, which allows the sensor interface to react to changing ambient conditions and makes it more robust. Furthermore, the design requirements of the analog circuit components can be drastically reduced since not all errors need to be fully compensated in the analog domain. The introduced approach is demonstrated by correcting different gain- and offset-errors in a 65 nm CMOS sensor interface.

This paper presents a new compact low supply current reference and a simulation-based design procedure to establish the circuit parameters quickly and efficiently. To verify the proposed design procedure, two sub 1 V example circuits for two different reference current values (80 nA and 800 nA) were designed and simulated using 0.35 μm CMOS technology. The circuits are robust against supply voltage variation without the need for external bandgap. A line sensitivity of approximately 1-2%/V over the supply voltage range from sub 1 V is achieved in both cases. The simulated temperature coefficient (TC) values are 93 ppm/ C and 197 ppm/° C in the temperature range from 0°C to 120° C for the 800 nA and 80 nA references, respectively.

Efficient signal processing takes a key role in application-specific circuit design. For instance, future mobile communication standards, e.g., high-performance industrial mobile communication, require high data rates, low latency and/or high energy-efficiency. Hence, sophisticated algorithms and computing schemes must be explored to satisfy these challenging constraints. In this paper we leverage the paradigm of approximate computing to enable hardware-efficient QR-decomposition for channel pre-coding. For an efficient computation of the Givens-Rotation, bivariate, non-linear numeric functions are taken into account. An effective design method is introduced leading to highly adapted (special-purpose) functions. For evaluation, our work is tested with different configurations in a Tomlinson-Harashima pre-coding downlink environment. In addition, a corresponding HDL implementation is set up and logic and physical CMOS synthesis is performed. The comparison to actual references prove our work to be a powerful approach for future mobile communication systems.

This paper presents an 8 channel neural stimulator ASIC for biphasic stimulation of the visual cortex, realized in a 0.35 μm AMS HV process. Each channel is composed of an SPI interface, an 8-bit current digital-to-analog converter (DAC) and 120 V compliant HV output stage. Thus it is possible to deliver to the tissue arbitrary current waveforms with amplitudes up to ±10.24 mA with 40 μA steps. According to the simulation results the maximum differential non-linearity is equal to 0.27 LSB. The on board current reference provides the output current of 16 μA with the variation of 90 ppm/°C in the temperature range of 0-85° C. While the anodic and cathodic currents mismatch does not exceed 13 μA. The HV output interface of the ASIC was previously fabricated and measured. The measured interpulse leakage current does not exceed 60 pA.

The aim of this study is to present the first compression and reconstruction methodology based on patch ordering inpainting algorithm for monitoring neural activity. This novel in-painting approach is especially important for the technical realization of implantable neural measurement systems (NMS) since they are subject to strict resource limitations as area and energy consumption. Intersection masks with center square as well as random-based masks are utilized for suitable neural data compression considering the patch ordering inpainting. The proposed inpainting methodology outperforms the structure-based inpainting algorithm and often applied Compressed Sensing strategy with regard to reconstruction quality of the real measured neural signals. These algorithms focus on complexity reduction according to hardware on implantable NMS. At high degrees of compression, the patch ordering inpainting yields well-suited or equal reconstruction results in contrast to JPEG or JPEG2000, respectively.

Scaled down analog integrated circuits are prone to degradation. This necessitates an online degradation monitoring and sophisticated analysis of degradation for this circuitry. Voltage reference sources such as beta-multiplier are commonly used circuits to set the operating points for downstream circuitry. Thus, the degradation of these sources are crucial for the overall degradation. In this paper the simulation results of the degradation analysis of a beta-multiplier circuit including the startup circuit, implemented in a 65nm CMOS technology, considering the temperature, are shown. A new approach for online degradation monitoring is introduced, utilizing startup circuit components to ensure minimal area and power overhead.

Inverters are one of the most basic logic blocks and exhibit a strong temperature dependency. Additionally, degradation in CMOS transistors affects the performance of circuits over time and is strongly dependent on temperature during circuit operation. In order to design robust and reliable ring oscillators and time to digital converters, both temperature dependencies have to be considered. This work introduces a circuit design for a robust and resilient inverter and an analysis on its temperature-dependent aging characteristic. The implemented inverter is driven by a common-source amplifier to achieve high robustness against temperature variation and aging effects. Based on this, circuit designs for a ring oscillator and an inverter-based delay line for a time to digital converter has been implemented. The results show that the deviation of the delay for an inverter can be minimized from 13.2% for conventional inverter design to less than 2% for the temperature-and aging-resistant design over a wide temperature range from -40° C to 150° C and a stress time of ten years.

The design and fabrication of fully-implantable neural measurement systems has been enabled by the continuous miniaturization and increasing integration density of modern CMOS technologies. The use of CMOS processes with small structure sizes benefits the energy consumption and the functionality of modern neural recording systems. However, the miniaturization increases the impact of degradation effects as well as the influence of variations. New EDA and modeling approaches have to be investigated in order to enable designers to simulate these effects already during the design phase of complex safety-critical applications. The aim of this paper is to present a new approach for the variability- and aging-aware behavioral model generation of analog components. The modeling is demonstrated on a neural amplifier topology in order to show the proposed design flow. For the investigated amplifier a simulation speedup of 110× compared to transistor level simulation could be obtained by still achieving a small error in mean value and standard deviation of the modeled performances. The variability-and aging-aware modeling is applied to an analog recording front-end as part of a neural measurement implant and enables the analysis of the expected system reliability over time. For the detection of neural action potentials a decrease in system performance of about 0.26 % due to aging influence is observed.

The recording of neural activities has turned out to be a promising approach to understand the basic function of specific brain parts like the visual or motor cortex. However, the development and design of advanced neural recording systems is very challenging since the number of parallel measurement channels increases continuously. Beside the analog recording channels digital preprocessing becomes mandatory to handle the corresponding amount of data and to adapt this data to the available transmission bandwidth. In this paper we present the design as well as the behavioral modeling of an analog recording front-end. Simulation and measurement results demonstrate the performances of the system for recording neural signals. Since simulation of this analog front-end is very time consuming but essential for large fully-integrated designs, a mixed-signal model approach is introduced that enables a significant simulation acceleration of integrated and external analog front-ends. The simulation can be accelerated by a factor of up to 22.2 for a single front-end. The proposed system has been fabricated in a 0.35 μm CMOS technology and performances have been measured. This demonstrates that the behavioral model is compatible to the transistor level design. A neural spike detector shows the transient performance of the modeled design on real input stimuli.

NBTI and HCI are not only present in digital circuits but also in analog circuitry. Integrated circuit amplifiers as used in neural measurement systems (NMS) need to be resistive against degradation since these systems cannot be replaced easily. A topology driven design methodology to increase the reliability of amplifiers used for intracortical neural recording has been proposed in this work. This approach leads to a decrease in degradation for some system performances by a factor of three. It has been shown that the degradation of a circuit is highly dependent on the selected current mirror and biasing circuit.

This paper presents a fully implantable neural recording system for the simultaneous recording of 128 channels. The electrocorticography (ECoG) signals are sensed with 128 gold electrodes embedded in a 10 µm thick polyimide foil. The signals are picked up by eight amplifier array ICs and digitized with a resolution of 16 bit at 10 kHz. The digitized measurement data is processed in a reconfigurable digital ASIC, which is fabricated in a 0.35 µm CMOS technology and occupies an area of 2.8×2.8mm2. After data reduction, the measurement data is fed into a transceiver IC, which transmits the data with up to 495 kbit/s to a base station, using an RF loop antenna on a flexible PCB. The power consumption of 84mW is delivered via inductive coupling from the base station.

In this paper we propose a QR-decomposition hardware implementation that processes complex calculations in the logarithmic number system. Thus, low complexity numeric format converters are installed, using nonuniform piecewise and multiplier-less function approximation. The proposed algorithm is simulated with several different configurations in a downlink precoding environment for 4×4 and 8×8 multi-antenna wireless communication systems. In addition, the results are compared to default CORDIC-based architectures. In a second step, HDL implementation as well as logical and physical CMOS synthesis are performed. The comparison to actual references highlight our approach as highly efficient in terms of hardware complexity and accuracy.

The combination of OFDM with joint pre-processing in adaptive multi-antenna systems offers both an ease of equalization in frequency-selective channels and keeping the signal processing at the mobile stations simple. In addition, the spatial dimension can be efficiently exploited to ensure high system throughput. With the utilization of higher-order modulation the performance of the system is highly sensitive to multiple access interference and nonorthogonal subchannels due to hardware impairments or insufficient adaptation to the current channel conditions. A further source of error in TDD systems are the non-reciprocal transceivers inhibiting the baseband-to-baseband channel reciprocity required for accurate channel state acquisition based on the uplink channel estimate. In this paper, measurement results of a low-cost hardware-based calibration are presented and the drawbacks are discussed leading to the utilization of a recently introduced relative calibration. The latter is applied to an OFDM system and achieves or at least approximates the baseband-to-baseband reciprocity. Thus, it enables the link adaptation using the uplink channel state information. Furthermore, preliminary hardware implementations of the relative calibration running on a real-time system show accurate results.

Time and frequency synchronisation are significant parts of the cell-search procedure and one of the first processing blocks within a mobile communication system. Particularly for an OFDM transmission within an initial synchronisation process, the algorithm has to deal with carrier frequency offsets up to several subcarrier spacings. To be able to still operate under those conditions, the cell-search procedure consists of different processing steps, combined in a hybrid algorithm. Beside good performance properties, hybrid algorithms lead to a high computational demand and implementation effort. To overcome these challenges, flexible architectures, which are able to select the most suitable algorithm during runtime, are the base for an efficient hardware realization. In this paper, as an example, we are introducing an hybrid initial synchronisation algorithm for an LTE-system, which still operates under the effect of a carrier frequency offset greater than the subcarrier spacing. Consecutively, we are showing a reconfigurable architecture as well as the results of an FPGA implementation of the time synchronisation part of that algorithm. The architecture is able to switch between different correlators, namely a reverse-auto, a cross- and a CP-based auto-correlation during runtime, which enables a flexible and low complexity realization of the computational complex synchronisation process.

Since Multiple Input Multiple Output (MIMO) transmission has become more and more popular for current and future mobile communication systems, MIMO detection is a big issue. Linear detection algorithms are less complex and well understood but their BER performance is limited. ML detectors achieve the optimum result but have exponential computational complexity. Hence, iterative tree-search algorithms like the sphere decoder or the K-Best detector, which reduce the computational complexity, has become a major topic in research. In this paper a modified K+-Best detector is introduced which is able to achieve the BER performance of a common K-Best detector with K=12, by using a sorting algorithm for K=8. This novel sorting approach based on Batchers Odd-Even Mergesort is less complex compared to other parallel sorting designs and saves valuable hardware resources. Due to an efficient implementation the throughput of the detector is about 455 Mbit/s which is twice as high as the LTE peak data rate of 217.6 Mbit/s for a 16-QAM modulated signal. In this paper the architecture and the implementation issues are demonstrated in detail and the BER performance of the K+-Best FPGA implementation is shown.

To meet the requirements of modern, high throughput communication systems, like the 3GPP Long Term Evolution, which aims to achieve a peak throughput of 100 Mbit/s in the downlink and 50 Mbit/s in the uplink, MIMO is a key technology. Therefore, efficient MIMO detection algorithms have become of major interest. Iterative tree-search detectors offer a good trade-off between the computational complexity and the BER performance. All these detectors assume a QR decomposed channel matrix to transform the Maximum Likelihood problem into a tree structure and to define a criterion to prune branches early. This criterion can be described by the Partial Euclidean Distance. In this paper we consider an iterative tree-search detector, namely a K-best detector, in combination with a specific QR-decomposition algorithm to formulate a Modified Partial Euclidean Distance and to avoid square roots and divisions, which normally appear due to the QR-decomposition. Hence, in opposite to an usual, separate algorithm optimization, a combined optimization is described.

This poster shows the work-in-progress results of an effective method for predicting the residual battery energy in WSN nodes including the battery behavior. This method uses a hybrid approach consisting of a deterministic part by counting credit points for any operation of the sensor node and a model-based State-of-Charge (SoC) estimation based on battery voltage and temperature. It is applied for Li-Ion accumulators on modified Tmote Sky motes. For demonstration purposes the method is used for cluster head selection in a cluster-based topology formation algorithm to ensure equal distribution of the cluster head role among the network nodes based on the residual energy.

Signal-to-noise ratio is an important parameter in many receivers. In this contribution, we derive a fixed-point equation whose solution coincides with the maximum-likelihood (ML) estimate of the amplitude of a binary phase-shift keying modulated signal and the variance of the additive white Gaussian noise. The resulting fixed-point equation is efficiently solved in a few iterations.

A word oriented memory Built-In Self-Repair (BISR) methodology is described without modifying the memory module. Faulty addresses and its data are stored in the redundancy logic immediately after its detection during test. Fuse boxes can be connected via scan registers to the redundancy logic.

Numerical algorithms for signal processing and control are quite often constructed by intuition. When the system to be designed contains algebraic or other invariants, then these constraints can be exploited to find appropriate transformations. The transformations in system theory are usually Lie groups. One has to find Lie groups which are consistent with the invariants. We show how this point of view can be applied to construct pole placement algorithms for symmetric and skew-symmetric realizations. However, Lie group theory only reveals the appropriate transformations but is not able to reduce the design process to a trivial task. The problem discussed here also shows this limitation.

The Jacobi algorithm for eigenvalue calculation of symmetric matrices can be performed with a CORDIC algorithm as its basic module. Recently, a simplified Jacobi algorithm, by employing approximate rotations based on CORDIC rotations, was proposed. It fully exploits the binary data structure and reduces the overall computational cost significantly. In this paper an error analysis of the approximate CORDIC-based Jacobi algorithm and the conventional CORDIC-based Jacobi algorithm is performed. The new algorithm behaves numerically better than the conventional CORDIC-based Jacobi algorithm for fixed as well as floating point arithmetic.>

A VLSI-suited processor array is presented that performs a Jacobi-like parallel algorithm for computing the real Schur decomposition of real nonsymmetric (n/spl times/n) matrices. The array consists of n/sup 2//4 processor cells which only perform exchange operations and elementary (2/spl times/2) plane rotations. The underlying algorithm iterates on dense matrices, i.e., the matrices need not to be reduced to some canonical form in advance. The iteration algorithm is derived by a problem adapted discretization process of an equivalent dynamical system. The dynamical system belongs to the class of isospectral matrix flow equations, i.e. a matrix valued differential equation, whose time evolution converges for t/spl rarr//spl infin/ to upper quasi triangular form. The integration scheme is performed by computing some highly regular orthogonal matrix-matrix multiplications.>

In the past, there have been several attempts to relate Hamiltonian equations, which describe conservative systems, to electrical networks. In control theory the ideas of Hamiltonian systems were expanded to affine Hamiltonian systems with feedback that are input/output systems with Hamiltonian vectorfields. In this paper the principles of affine Hamiltonian systems are applied to a class of electrical networks. It is shown that voltage and current coordinates admit a Poisson structure and how input/output Poisson systems with feedback are related to electrical networks.>

A very fast Jacobi-like algorithm for the parallel solution of symmetric eigenvalue problems is proposed. It becomes possible by not focusing on the realization of the Jacobi rotation with a CORDIC processor, but by applying approximate rotations and adjusting them to single steps of the CORDIC algorithm, i.e., only one angle of the CORDIC angle sequence defines the Jacobi rotation in each step. This angle can be determined by some shift, add and compare operations. Although only linear convergence is obtained for the most simple version of the new algorithm, the overall operation count (shifts and adds) decreases dramatically. A slow increase of the number of involved CORDIC angles during the runtime retains quadratic convergence.>

The basic nonlinear operation in median filtering is a sorting of the input data vector. An analog structure for this filtering operation is presented. The sorting operation is embedded in a matrix-valued ordinary differential equation (ODE). The data to be sorted serve as initial values for the ODE. To induce the dynamics of the system a small perturbation is necessary. The circuit structure for the analog median filter consists of basic processing cells containing multipliers, integrators, and adders, arranged in an one-dimensional array. All connections are local only and no external control is necessary.>